From: Sam Ravnborg <sam@ravnborg.org>
To: Maxime Ripard <maxime@cerno.tech>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, David Airlie <airlied@linux.ie>,
dri-devel@lists.freedesktop.org, Chen-Yu Tsai <wens@csie.org>,
Rob Herring <robh+dt@kernel.org>,
Sean Paul <seanpaul@chromium.org>,
Thierry Reding <thierry.reding@gmail.com>,
Daniel Vetter <daniel.vetter@intel.com>,
Frank Rowand <frowand.list@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/4] drm/connector: Add data polarity flags
Date: Fri, 14 Feb 2020 17:13:59 +0100 [thread overview]
Message-ID: <20200214161359.GB18287@ravnborg.org> (raw)
In-Reply-To: <b541006fa0a1c34ac5f668dc561aa1598f8fd86c.1581682983.git-series.maxime@cerno.tech>
Hi Maxime.
On Fri, Feb 14, 2020 at 01:24:38PM +0100, Maxime Ripard wrote:
> Some LVDS encoders can change the polarity of the data signals being
> sent. Add a DRM bus flag to reflect this.
>
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> ---
> include/drm/drm_connector.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 221910948b37..9a08fe6ab7c2 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -330,6 +330,8 @@ enum drm_panel_orientation {
> * edge of the pixel clock
> * @DRM_BUS_FLAG_SHARP_SIGNALS: Set if the Sharp-specific signals
> * (SPL, CLS, PS, REV) must be used
> + * @DRM_BUS_FLAG_DATA_LOW: The Data signals are active low
> + * @DRM_BUS_FLAG_DATA_HIGH: The Data signals are active high
Reading the description of these falgs always confuses me.
In this case if neither bit 9 nor bit 10 is set then the data signals
are netiher active low nor active high.
So what can I then expect?
We have the same logic loophole for DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE
and DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE.
So it is not new, but can we do better here?
Sam
> */
> enum drm_bus_flags {
> DRM_BUS_FLAG_DE_LOW = BIT(0),
> @@ -349,6 +351,8 @@ enum drm_bus_flags {
> DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE = DRM_BUS_FLAG_SYNC_NEGEDGE,
> DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE = DRM_BUS_FLAG_SYNC_POSEDGE,
> DRM_BUS_FLAG_SHARP_SIGNALS = BIT(8),
> + DRM_BUS_FLAG_DATA_LOW = BIT(9),
> + DRM_BUS_FLAG_DATA_HIGH = BIT(10),
> };
>
> /**
> --
> git-series 0.9.1
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next prev parent reply other threads:[~2020-02-14 16:14 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-14 12:24 [PATCH 0/4] drm/sun4i: Support clock and data polarities on LVDS output Maxime Ripard
2020-02-14 12:24 ` [PATCH 1/4] drm/connector: Add data polarity flags Maxime Ripard
2020-02-14 16:13 ` Sam Ravnborg [this message]
2020-02-20 18:00 ` Maxime Ripard
2020-02-14 12:24 ` [PATCH 2/4] dt-bindings: panel: lvds: Add properties for clock and data polarities Maxime Ripard
2020-02-14 16:11 ` Sam Ravnborg
2020-02-20 17:57 ` Maxime Ripard
2020-02-19 23:12 ` Rob Herring
2020-02-14 12:24 ` [PATCH 3/4] drm/panel: lvds: Support data and clock polarity flags Maxime Ripard
2020-02-14 12:24 ` [PATCH 4/4] drm/sun4i: " Maxime Ripard
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