From: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
To: sameer.lattannavar@intel.com, jani.nikula@linux.intel.com,
daniel@ffwll.ch, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org, ville.syrjala@linux.intel.com,
daniels@collabora.com,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
David Airlie <airlied@linux.ie>
Cc: pankaj.laxminarayan.bharadiya@intel.com
Subject: [PATCH v2 3/5] drm/i915: Introduce scaling filter related registers and bit fields.
Date: Thu, 19 Mar 2020 15:51:01 +0530 [thread overview]
Message-ID: <20200319102103.28895-4-pankaj.laxminarayan.bharadiya@intel.com> (raw)
In-Reply-To: <20200319102103.28895-1-pankaj.laxminarayan.bharadiya@intel.com>
Introduce scaler registers and bit fields needed to configure the
scaling filter in prgrammed mode and configure scaling filter
coefficients.
changes since v1:
* None
changes since RFC:
* Parametrize scaler coeffient macros by 'set' (Ville)
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 48 +++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c53fe918be6..d40f12d2a6b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7205,6 +7205,7 @@ enum {
#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
#define PS_FILTER_MASK (3 << 23)
#define PS_FILTER_MEDIUM (0 << 23)
+#define PS_FILTER_PROGRAMMED (1 << 23)
#define PS_FILTER_EDGE_ENHANCE (2 << 23)
#define PS_FILTER_BILINEAR (3 << 23)
#define PS_VERT3TAP (1 << 21)
@@ -7219,6 +7220,10 @@ enum {
#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
#define PS_PLANE_Y_SEL_MASK (7 << 5)
#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
+#define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
+#define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
+#define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
+#define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1)
#define _PS_PWR_GATE_1A 0x68160
#define _PS_PWR_GATE_2A 0x68260
@@ -7281,6 +7286,25 @@ enum {
#define _PS_ECC_STAT_2B 0x68AD0
#define _PS_ECC_STAT_1C 0x691D0
+#define _PS_COEF_SET0_INDEX_1A 0x68198
+#define _PS_COEF_SET0_INDEX_2A 0x68298
+#define _PS_COEF_SET0_INDEX_1B 0x68998
+#define _PS_COEF_SET0_INDEX_2B 0x68A98
+#define _PS_COEF_SET1_INDEX_1A 0x681A0
+#define _PS_COEF_SET1_INDEX_2A 0x682A0
+#define _PS_COEF_SET1_INDEX_1B 0x689A0
+#define _PS_COEF_SET1_INDEX_2B 0x68AA0
+#define PS_COEE_INDEX_AUTO_INC (1 << 10)
+
+#define _PS_COEF_SET0_DATA_1A 0x6819C
+#define _PS_COEF_SET0_DATA_2A 0x6829C
+#define _PS_COEF_SET0_DATA_1B 0x6899C
+#define _PS_COEF_SET0_DATA_2B 0x68A9C
+#define _PS_COEF_SET1_DATA_1A 0x681A4
+#define _PS_COEF_SET1_DATA_2A 0x682A4
+#define _PS_COEF_SET1_DATA_1B 0x689A4
+#define _PS_COEF_SET1_DATA_2B 0x68AA4
+
#define _ID(id, a, b) _PICK_EVEN(id, a, b)
#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
_ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
@@ -7310,6 +7334,30 @@ enum {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
+#define _SKL_PS_COEF_INDEX_SET0(pipe, id) _ID(pipe, \
+ _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A), \
+ _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B))
+
+#define _SKL_PS_COEF_INDEX_SET1(pipe, id) _ID(pipe, \
+ _ID(id, _PS_COEF_SET1_INDEX_1A, _PS_COEF_SET1_INDEX_2A), \
+ _ID(id, _PS_COEF_SET1_INDEX_1B, _PS_COEF_SET1_INDEX_2B))
+
+#define _SKL_PS_COEF_DATA_SET0(pipe, id) _ID(pipe, \
+ _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A), \
+ _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B))
+
+#define _SKL_PS_COEF_DATA_SET1(pipe, id) _ID(pipe, \
+ _ID(id, _PS_COEF_SET1_DATA_1A, _PS_COEF_SET1_DATA_2A), \
+ _ID(id, _PS_COEF_SET1_DATA_1B, _PS_COEF_SET1_DATA_2B))
+
+#define SKL_PS_COEF_INDEX_SET(pipe, id, set) \
+ _MMIO_PIPE(set, _SKL_PS_COEF_INDEX_SET0(pipe, id), \
+ _SKL_PS_COEF_INDEX_SET1(pipe, id))
+
+#define SKL_PS_COEF_DATA_SET(pipe, id, set) \
+ _MMIO_PIPE(set, _SKL_PS_COEF_DATA_SET0(pipe, id), \
+ _SKL_PS_COEF_DATA_SET1(pipe, id))
+
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
--
2.23.0
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next prev parent reply other threads:[~2020-03-19 10:31 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-19 10:20 [PATCH v2 0/5] Introduce drm scaling filter property Pankaj Bharadiya
2020-03-19 10:20 ` [PATCH v2 1/5] drm: Introduce plane and CRTC scaling filter properties Pankaj Bharadiya
2020-03-23 14:21 ` Ville Syrjälä
2020-03-24 14:22 ` Laxminarayan Bharadiya, Pankaj
2020-03-19 10:21 ` [PATCH v2 2/5] drm/drm-kms.rst: Add plane and CRTC scaling filter property documentation Pankaj Bharadiya
2020-03-19 10:21 ` Pankaj Bharadiya [this message]
2020-03-23 14:39 ` [PATCH v2 3/5] drm/i915: Introduce scaling filter related registers and bit fields Ville Syrjälä
2020-03-24 14:36 ` Laxminarayan Bharadiya, Pankaj
2020-03-24 16:43 ` Ville Syrjälä
2020-03-19 10:21 ` [PATCH v2 4/5] drm/i915/display: Add Nearest-neighbor based integer scaling support Pankaj Bharadiya
2020-03-23 14:41 ` Ville Syrjälä
2020-03-19 10:21 ` [PATCH v2 5/5] drm/i915: Enable scaling filter for plane and CRTC Pankaj Bharadiya
2020-03-23 14:47 ` Ville Syrjälä
2020-03-24 15:32 ` Laxminarayan Bharadiya, Pankaj
2020-03-24 16:46 ` Ville Syrjälä
2020-03-26 15:15 ` Bharadiya,Pankaj
2020-03-26 15:36 ` Ville Syrjälä
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