From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [PATCH 0/4] drm/i915: Fix older platforms
Date: Wed, 21 Apr 2021 18:33:57 +0300 [thread overview]
Message-ID: <20210421153401.13847-1-ville.syrjala@linux.intel.com> (raw)
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fix a div-by-zero on gen2, and make the L-shaped memory detection
actually work on cl/ctg. Atm the SWIZZLE_UNKNOWN stuff just trips
some GEM_BUG_ONs. This doesn't fix those but since I populate all
my memory channels symmetrically I get to avoid the GEM_BUG_ONs
by correctly detecting that I don't have an L-shaped memory
configuration.
Ville Syrjälä (4):
drm/i915: Avoid div-by-zero on gen2
drm/i915: Read C0DRB3/C1DRB3 as 16 bits again
drm/i915: Give C0DRB3/C1DRB3 a _BW suffix
drm/i915: Rewrite CL/CTG L-shaped memory detection
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 19 ++++++++++---------
drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
4 files changed, 29 insertions(+), 16 deletions(-)
--
2.26.3
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next reply other threads:[~2021-04-21 15:34 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-21 15:33 Ville Syrjala [this message]
2021-04-21 15:33 ` [PATCH 1/4] drm/i915: Avoid div-by-zero on gen2 Ville Syrjala
2021-04-21 15:33 ` [PATCH 2/4] drm/i915: Read C0DRB3/C1DRB3 as 16 bits again Ville Syrjala
2021-04-21 15:34 ` [PATCH 3/4] drm/i915: Give C0DRB3/C1DRB3 a _BW suffix Ville Syrjala
2021-04-21 15:34 ` [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection Ville Syrjala
2021-04-22 9:49 ` [Intel-gfx] " Daniel Vetter
2021-04-22 13:11 ` Ville Syrjälä
2021-04-26 16:08 ` Daniel Vetter
2021-04-26 17:18 ` Ville Syrjälä
2021-04-27 8:58 ` Daniel Vetter
2021-10-04 10:36 ` Ville Syrjälä
2021-04-22 18:51 ` Ville Syrjälä
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