From: Liu Ying <victor.liu@nxp.com>
To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org
Cc: martin.kepplinger@puri.sm, agx@sigxcpu.org,
jernej.skrabec@gmail.com, narmstrong@baylibre.com,
airlied@linux.ie, s.hauer@pengutronix.de, jonas@kwiboo.se,
robert.foss@linaro.org, kishon@ti.com, vkoul@kernel.org,
robh+dt@kernel.org, Laurent.pinchart@ideasonboard.com,
andrzej.hajda@intel.com, robert.chiras@nxp.com,
krzk+dt@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de,
linux-imx@nxp.com
Subject: [PATCH v7 4/5] dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp
Date: Thu, 14 Apr 2022 14:48:57 +0800 [thread overview]
Message-ID: <20220414064858.405096-5-victor.liu@nxp.com> (raw)
In-Reply-To: <20220414064858.405096-1-victor.liu@nxp.com>
Add support for Mixel MIPI DPHY + LVDS PHY combo IP
as found on Freescale i.MX8qxp SoC.
Cc: Guido Günther <agx@sigxcpu.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Add Rob's and Guido's R-b tags.
v2->v3:
* No change.
v1->v2:
* Add the binding for i.MX8qxp Mixel combo PHY based on the converted binding.
(Guido)
.../bindings/phy/mixel,mipi-dsi-phy.yaml | 41 +++++++++++++++++--
1 file changed, 38 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml
index c34f2e6d6bd5..786cfd71cb7e 100644
--- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml
@@ -14,10 +14,14 @@ description: |
MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
electrical signals for DSI.
+ The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
+ in either MIPI-DSI PHY mode or LVDS PHY mode.
+
properties:
compatible:
enum:
- fsl,imx8mq-mipi-dphy
+ - fsl,imx8qxp-mipi-dphy
reg:
maxItems: 1
@@ -40,6 +44,11 @@ properties:
"#phy-cells":
const: 0
+ fsl,syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ A phandle which points to Control and Status Registers(CSR) module.
+
power-domains:
maxItems: 1
@@ -48,12 +57,38 @@ required:
- reg
- clocks
- clock-names
- - assigned-clocks
- - assigned-clock-parents
- - assigned-clock-rates
- "#phy-cells"
- power-domains
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mq-mipi-dphy
+ then:
+ properties:
+ fsl,syscon: false
+
+ required:
+ - assigned-clocks
+ - assigned-clock-parents
+ - assigned-clock-rates
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8qxp-mipi-dphy
+ then:
+ properties:
+ assigned-clocks: false
+ assigned-clock-parents: false
+ assigned-clock-rates: false
+
+ required:
+ - fsl,syscon
+
additionalProperties: false
examples:
--
2.25.1
next prev parent reply other threads:[~2022-04-14 6:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-14 6:48 [PATCH v7 0/5] phy: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support Liu Ying
2022-04-14 6:48 ` [PATCH v7 1/5] drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_mode_set() Liu Ying
2022-04-14 7:47 ` Guido Günther
2022-04-14 6:48 ` [PATCH v7 2/5] phy: Add LVDS configuration options Liu Ying
2022-04-14 6:48 ` [PATCH v7 3/5] dt-bindings: phy: Convert mixel, mipi-dsi-phy to json-schema Liu Ying
2022-04-14 6:48 ` Liu Ying [this message]
2022-04-14 6:48 ` [PATCH v7 5/5] phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support Liu Ying
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220414064858.405096-5-victor.liu@nxp.com \
--to=victor.liu@nxp.com \
--cc=Laurent.pinchart@ideasonboard.com \
--cc=agx@sigxcpu.org \
--cc=airlied@linux.ie \
--cc=andrzej.hajda@intel.com \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=jernej.skrabec@gmail.com \
--cc=jonas@kwiboo.se \
--cc=kernel@pengutronix.de \
--cc=kishon@ti.com \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-imx@nxp.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=martin.kepplinger@puri.sm \
--cc=narmstrong@baylibre.com \
--cc=robert.chiras@nxp.com \
--cc=robert.foss@linaro.org \
--cc=robh+dt@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=shawnguo@kernel.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).