From: Claire Chang <tientzu@chromium.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: heikki.krogerus@linux.intel.com,
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Subject: Re: [PATCH v5 16/16] of: Add plumbing for restricted DMA pool
Date: Tue, 27 Apr 2021 00:38:08 +0800 [thread overview]
Message-ID: <CALiNf28ExE8OLsuDaN9nC=eAi-iG0rct_TJCCxAcWW4+_pdj2g@mail.gmail.com> (raw)
In-Reply-To: <03c5bc8a-3965-bf1d-01a4-97d074dfbe2b@arm.com>
On Fri, Apr 23, 2021 at 9:35 PM Robin Murphy <robin.murphy@arm.com> wrote:
>
> On 2021-04-22 09:15, Claire Chang wrote:
> > If a device is not behind an IOMMU, we look up the device node and set
> > up the restricted DMA when the restricted-dma-pool is presented.
> >
> > Signed-off-by: Claire Chang <tientzu@chromium.org>
> > ---
> > drivers/of/address.c | 25 +++++++++++++++++++++++++
> > drivers/of/device.c | 3 +++
> > drivers/of/of_private.h | 5 +++++
> > 3 files changed, 33 insertions(+)
> >
> > diff --git a/drivers/of/address.c b/drivers/of/address.c
> > index 54f221dde267..fff3adfe4986 100644
> > --- a/drivers/of/address.c
> > +++ b/drivers/of/address.c
> > @@ -8,6 +8,7 @@
> > #include <linux/logic_pio.h>
> > #include <linux/module.h>
> > #include <linux/of_address.h>
> > +#include <linux/of_reserved_mem.h>
> > #include <linux/pci.h>
> > #include <linux/pci_regs.h>
> > #include <linux/sizes.h>
> > @@ -1109,6 +1110,30 @@ bool of_dma_is_coherent(struct device_node *np)
> > }
> > EXPORT_SYMBOL_GPL(of_dma_is_coherent);
> >
> > +int of_dma_set_restricted_buffer(struct device *dev)
> > +{
> > + struct device_node *node;
> > + int count, i;
> > +
> > + if (!dev->of_node)
> > + return 0;
> > +
> > + count = of_property_count_elems_of_size(dev->of_node, "memory-region",
> > + sizeof(phandle));
> > + for (i = 0; i < count; i++) {
> > + node = of_parse_phandle(dev->of_node, "memory-region", i);
> > + /* There might be multiple memory regions, but only one
> > + * restriced-dma-pool region is allowed.
> > + */
>
> What's the use-case for having multiple regions if the restricted pool
> is by definition the only one accessible?
There might be a device coherent pool (shared-dma-pool) and
dma_alloc_attrs might allocate memory from that pool [1].
I'm not sure if it makes sense to have another device coherent pool
while using restricted DMA pool though.
[1] https://elixir.bootlin.com/linux/v5.12/source/kernel/dma/mapping.c#L435
>
> Robin.
>
> > + if (of_device_is_compatible(node, "restricted-dma-pool") &&
> > + of_device_is_available(node))
> > + return of_reserved_mem_device_init_by_idx(
> > + dev, dev->of_node, i);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > /**
> > * of_mmio_is_nonposted - Check if device uses non-posted MMIO
> > * @np: device node
> > diff --git a/drivers/of/device.c b/drivers/of/device.c
> > index c5a9473a5fb1..d8d865223e51 100644
> > --- a/drivers/of/device.c
> > +++ b/drivers/of/device.c
> > @@ -165,6 +165,9 @@ int of_dma_configure_id(struct device *dev, struct device_node *np,
> >
> > arch_setup_dma_ops(dev, dma_start, size, iommu, coherent);
> >
> > + if (!iommu)
> > + return of_dma_set_restricted_buffer(dev);
> > +
> > return 0;
> > }
> > EXPORT_SYMBOL_GPL(of_dma_configure_id);
> > diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h
> > index d717efbd637d..e9237f5eff48 100644
> > --- a/drivers/of/of_private.h
> > +++ b/drivers/of/of_private.h
> > @@ -163,12 +163,17 @@ struct bus_dma_region;
> > #if defined(CONFIG_OF_ADDRESS) && defined(CONFIG_HAS_DMA)
> > int of_dma_get_range(struct device_node *np,
> > const struct bus_dma_region **map);
> > +int of_dma_set_restricted_buffer(struct device *dev);
> > #else
> > static inline int of_dma_get_range(struct device_node *np,
> > const struct bus_dma_region **map)
> > {
> > return -ENODEV;
> > }
> > +static inline int of_dma_get_restricted_buffer(struct device *dev)
> > +{
> > + return -ENODEV;
> > +}
> > #endif
> >
> > #endif /* _LINUX_OF_PRIVATE_H */
> >
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next prev parent reply other threads:[~2021-04-26 16:44 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-22 8:14 [PATCH v5 00/16] Restricted DMA Claire Chang
2021-04-22 8:14 ` [PATCH v5 01/16] swiotlb: Fix the type of index Claire Chang
2021-04-22 8:14 ` [PATCH v5 02/16] swiotlb: Refactor swiotlb init functions Claire Chang
2021-04-22 8:14 ` [PATCH v5 03/16] swiotlb: Refactor swiotlb_create_debugfs Claire Chang
2021-04-22 8:14 ` [PATCH v5 04/16] swiotlb: Add DMA_RESTRICTED_POOL Claire Chang
2021-04-22 8:14 ` [PATCH v5 05/16] swiotlb: Add restricted DMA pool initialization Claire Chang
2021-04-23 11:34 ` Steven Price
2021-04-26 16:37 ` Claire Chang
2021-04-28 9:50 ` Steven Price
2021-04-22 8:14 ` [PATCH v5 06/16] swiotlb: Add a new get_io_tlb_mem getter Claire Chang
2021-04-22 8:14 ` [PATCH v5 07/16] swiotlb: Update is_swiotlb_buffer to add a struct device argument Claire Chang
2021-04-22 8:15 ` [PATCH v5 08/16] swiotlb: Update is_swiotlb_active " Claire Chang
2021-04-23 13:31 ` Robin Murphy
2021-04-26 16:37 ` Claire Chang
2021-04-22 8:15 ` [PATCH v5 09/16] swiotlb: Bounce data from/to restricted DMA pool if available Claire Chang
2021-04-22 8:15 ` [PATCH v5 10/16] swiotlb: Move alloc_size to find_slots Claire Chang
2021-04-22 8:15 ` [PATCH v5 11/16] swiotlb: Refactor swiotlb_tbl_unmap_single Claire Chang
2021-04-22 8:15 ` [PATCH v5 12/16] dma-direct: Add a new wrapper __dma_direct_free_pages() Claire Chang
2021-04-22 8:15 ` [PATCH v5 13/16] swiotlb: Add restricted DMA alloc/free support Claire Chang
2021-04-22 8:15 ` [PATCH v5 14/16] dma-direct: Allocate memory from restricted DMA pool if available Claire Chang
2021-04-23 13:46 ` Robin Murphy
2021-05-03 14:26 ` Claire Chang
2021-04-22 8:15 ` [PATCH v5 15/16] dt-bindings: of: Add restricted DMA pool Claire Chang
2021-04-22 8:15 ` [PATCH v5 16/16] of: Add plumbing for " Claire Chang
2021-04-23 2:52 ` Claire Chang
2021-04-23 13:35 ` Robin Murphy
2021-04-26 16:38 ` Claire Chang [this message]
2021-05-10 9:53 ` [PATCH v5 00/16] Restricted DMA Claire Chang
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