From: Thomas Zimmermann <tzimmermann@suse.de>
To: KuoHsiang Chou <kuohsiang_chou@aspeedtech.com>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Cc: airlied@linux.ie, jenmin_yuan@aspeedtech.com,
tommy_huang@aspeedtech.com, arc_sung@aspeedtech.com,
airlied@redhat.com
Subject: Re: [PATCH V3] drm/ast: Disable fast reset after DRAM initial
Date: Mon, 29 Mar 2021 11:17:27 +0200 [thread overview]
Message-ID: <b0e960ee-b987-69f7-13fd-0270c347ad5e@suse.de> (raw)
In-Reply-To: <20210319092340.140267-1-kuohsiang_chou@aspeedtech.com>
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Hi,
I cannot apply this patch. The error is shown below. Which tree do you
use? Can you please move to drm-misc-next?
Applying: drm/ast: Disable fast reset after DRAM initial
error: sha1 information is lacking or useless
(drivers/gpu/drm/ast/ast_drv.h).
error: could not build fake ancestor
Patch failed at 0001 drm/ast: Disable fast reset after DRAM initial
hint: Use 'git am --show-current-patch=diff' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
dim: ERROR: git apply-mbox failed
Best regards
Thomas
Am 19.03.21 um 10:23 schrieb KuoHsiang Chou:
> [Bug][AST2500]
>
> V1:
> When AST2500 acts as stand-alone VGA so that DRAM and DVO initialization
> have to be achieved by VGA driver with P2A (PCI to AHB) enabling.
> However, HW suggests disable Fast reset mode after DRAM initializaton,
> because fast reset mode is mainly designed for ARM ICE debugger.
> Once Fast reset is checked as enabling, WDT (Watch Dog Timer) should be
> first enabled to avoid system deadlock before disable fast reset mode.
>
> V2:
> Use to_pci_dev() to get revision of PCI configuration.
>
> V3:
> If SCU00 is not unlocked, just enter its password again.
> It is unnecessary to clear AHB lock condition and restore WDT default
> setting again, before Fast-reset clearing.
>
> Signed-off-by: KuoHsiang Chou <kuohsiang_chou@aspeedtech.com>
> ---
> drivers/gpu/drm/ast/ast_drv.h | 1 +
> drivers/gpu/drm/ast/ast_main.c | 5 +++
> drivers/gpu/drm/ast/ast_post.c | 68 +++++++++++++++++++++-------------
> 3 files changed, 48 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h
> index da6dfb677540..a2cf5fef2399 100644
> --- a/drivers/gpu/drm/ast/ast_drv.h
> +++ b/drivers/gpu/drm/ast/ast_drv.h
> @@ -320,6 +320,7 @@ bool ast_is_vga_enabled(struct drm_device *dev);
> void ast_post_gpu(struct drm_device *dev);
> u32 ast_mindwm(struct ast_private *ast, u32 r);
> void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
> +void ast_patch_ahb_2500(struct ast_private *ast);
> /* ast dp501 */
> void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
> bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
> diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
> index 3775fe26f792..0e4dfcc25623 100644
> --- a/drivers/gpu/drm/ast/ast_main.c
> +++ b/drivers/gpu/drm/ast/ast_main.c
> @@ -69,6 +69,7 @@ static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
> {
> struct device_node *np = dev->pdev->dev.of_node;
> struct ast_private *ast = to_ast_private(dev);
> + struct pci_dev *pdev = to_pci_dev(dev->dev);
> uint32_t data, jregd0, jregd1;
>
> /* Defaults */
> @@ -96,6 +97,10 @@ static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
> jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
> jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
> if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
> + /* Patch AST2500 */
> + if (((pdev->revision & 0xF0) == 0x40) && ((jregd0 & 0xC0) == 0))
> + ast_patch_ahb_2500(ast);
> +
> /* Double check it's actually working */
> data = ast_read32(ast, 0xf004);
> if (data != 0xFFFFFFFF) {
> diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
> index 8902c2f84bf9..4f194c5fd2c2 100644
> --- a/drivers/gpu/drm/ast/ast_post.c
> +++ b/drivers/gpu/drm/ast/ast_post.c
> @@ -2026,6 +2026,30 @@ static bool ast_dram_init_2500(struct ast_private *ast)
> return true;
> }
>
> +void ast_patch_ahb_2500(struct ast_private *ast)
> +{
> + u32 data;
> +
> + /* Clear bus lock condition */
> + ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
> + ast_moutdwm(ast, 0x1e600084, 0x00010000);
> + ast_moutdwm(ast, 0x1e600088, 0x00000000);
> + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
> + data = ast_mindwm(ast, 0x1e6e2070);
> + if (data & 0x08000000) { /* check fast reset */
> +
> + ast_moutdwm(ast, 0x1E785004, 0x00000010);
> + ast_moutdwm(ast, 0x1E785008, 0x00004755);
> + ast_moutdwm(ast, 0x1E78500c, 0x00000033);
> + udelay(1000);
> + }
> + do {
> + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
> + data = ast_mindwm(ast, 0x1e6e2000);
> + } while (data != 1);
> + ast_moutdwm(ast, 0x1e6e207c, 0x08000000); /* clear fast reset */
> +}
> +
> void ast_post_chip_2500(struct drm_device *dev)
> {
> struct ast_private *ast = to_ast_private(dev);
> @@ -2033,39 +2057,31 @@ void ast_post_chip_2500(struct drm_device *dev)
> u8 reg;
>
> reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
> - if ((reg & 0x80) == 0) {/* vga only */
> + if ((reg & 0xC0) == 0) {/* vga only */
> /* Clear bus lock condition */
> - ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
> - ast_moutdwm(ast, 0x1e600084, 0x00010000);
> - ast_moutdwm(ast, 0x1e600088, 0x00000000);
> - ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
> - ast_write32(ast, 0xf004, 0x1e6e0000);
> - ast_write32(ast, 0xf000, 0x1);
> - ast_write32(ast, 0x12000, 0x1688a8a8);
> - while (ast_read32(ast, 0x12000) != 0x1)
> - ;
> -
> - ast_write32(ast, 0x10000, 0xfc600309);
> - while (ast_read32(ast, 0x10000) != 0x1)
> - ;
> + ast_patch_ahb_2500(ast);
> +
> + /* Disable watchdog */
> + ast_moutdwm(ast, 0x1E78502C, 0x00000000);
> + ast_moutdwm(ast, 0x1E78504C, 0x00000000);
> + /* Reset USB port */
> + ast_moutdwm(ast, 0x1E6E2090, 0x20000000);
> + ast_moutdwm(ast, 0x1E6E2094, 0x00004000);
> + if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) {
> + ast_moutdwm(ast, 0x1E6E207C, 0x00800000);
> + mdelay(100);
> + ast_moutdwm(ast, 0x1E6E2070, 0x00800000);
> + }
> + /* Modify eSPI reset pin */
> + temp = ast_mindwm(ast, 0x1E6E2070);
> + if (temp & 0x02000000)
> + ast_moutdwm(ast, 0x1E6E207C, 0x00004000);
>
> /* Slow down CPU/AHB CLK in VGA only mode */
> temp = ast_read32(ast, 0x12008);
> temp |= 0x73;
> ast_write32(ast, 0x12008, temp);
>
> - /* Reset USB port to patch USB unknown device issue */
> - ast_moutdwm(ast, 0x1e6e2090, 0x20000000);
> - temp = ast_mindwm(ast, 0x1e6e2094);
> - temp |= 0x00004000;
> - ast_moutdwm(ast, 0x1e6e2094, temp);
> - temp = ast_mindwm(ast, 0x1e6e2070);
> - if (temp & 0x00800000) {
> - ast_moutdwm(ast, 0x1e6e207c, 0x00800000);
> - mdelay(100);
> - ast_moutdwm(ast, 0x1e6e2070, 0x00800000);
> - }
> -
> if (!ast_dram_init_2500(ast))
> drm_err(dev, "DRAM init failed !\n");
>
> --
> 2.18.4
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer
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next prev parent reply other threads:[~2021-03-29 9:17 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-18 8:57 [PATCH] drm/ast: Update the sequence of Clearing Fast-reset KuoHsiang Chou
2021-01-21 7:55 ` Thomas Zimmermann
2021-01-21 8:42 ` Kuo-Hsiang Chou
2021-03-19 9:23 ` [PATCH V3] drm/ast: Disable fast reset after DRAM initial KuoHsiang Chou
2021-03-29 9:17 ` Thomas Zimmermann [this message]
2021-03-31 6:56 ` Kuo-Hsiang Chou
2021-03-31 7:20 ` Thomas Zimmermann
2021-04-08 9:30 ` [PATCH v4] drm/ast: Fixed CVE for DP501 KuoHsiang Chou
2021-04-12 7:45 ` Thomas Zimmermann
2021-04-21 8:58 ` [PATCH v5] " KuoHsiang Chou
2021-04-27 11:01 ` Thomas Zimmermann
2021-04-29 9:21 ` Kuo-Hsiang Chou
2021-08-03 8:58 ` Thomas Zimmermann
2021-08-04 2:20 ` Kuo-Hsiang Chou
2021-05-07 9:27 ` [PATCH v4] drm/ast: Disable fast reset after DRAM initial KuoHsiang Chou
2021-05-26 10:24 ` Kuo-Hsiang Chou
2021-06-21 11:06 ` Kuo-Hsiang Chou
2021-06-21 12:46 ` Thomas Zimmermann
2021-06-23 8:02 ` Thomas Zimmermann
2021-07-09 8:09 ` [PATCH v5] " KuoHsiang Chou
2021-07-20 8:49 ` Thomas Zimmermann
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