From: Maxime Ripard <maxime@cerno.tech>
To: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
Eric Anholt <eric@anholt.net>
Cc: Tim Gover <tim.gover@raspberrypi.com>,
Dave Stevenson <dave.stevenson@raspberrypi.com>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
bcm-kernel-feedback-list@broadcom.com,
linux-rpi-kernel@lists.infradead.org,
Phil Elwell <phil@raspberrypi.com>,
linux-arm-kernel@lists.infradead.org,
Maxime Ripard <maxime@cerno.tech>
Subject: [PATCH v3 014/105] drm/vc4: Add support for the BCM2711 HVS5
Date: Wed, 27 May 2020 17:47:44 +0200 [thread overview]
Message-ID: <c466ef999819b8314d8046319a7a4c463884a137.1590594512.git-series.maxime@cerno.tech> (raw)
In-Reply-To: <cover.aaf2100bd7da4609f8bcb8216247d4b4e4379639.1590594512.git-series.maxime@cerno.tech>
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
The HVS found in the BCM2711 is slightly different from the previous
generations.
Most notably, the display list layout changes a bit, the LBM doesn't have
the same size and the formats ordering for some formats is swapped.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 24 +++-
drivers/gpu/drm/vc4/vc4_drv.h | 4 +-
drivers/gpu/drm/vc4/vc4_hvs.c | 16 ++-
drivers/gpu/drm/vc4/vc4_plane.c | 194 ++++++++++++++++++++++++---------
drivers/gpu/drm/vc4/vc4_regs.h | 67 +++++++++++-
5 files changed, 246 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 1208258ad3b2..591a10ae1950 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -551,6 +551,7 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ u32 dispctrl;
require_hvs_enabled(dev);
@@ -565,11 +566,24 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
* When feeding the transposer, we should operate in oneshot
* mode.
*/
- HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
- VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
- VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
- SCALER_DISPCTRLX_ENABLE |
- (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
+ dispctrl = SCALER_DISPCTRLX_ENABLE;
+
+ if (!vc4->hvs->hvs5)
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER_DISPCTRLX_HEIGHT) |
+ (vc4_state->feed_txp ?
+ SCALER_DISPCTRLX_ONESHOT : 0);
+ else
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER5_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER5_DISPCTRLX_HEIGHT) |
+ (vc4_state->feed_txp ?
+ SCALER5_DISPCTRLX_ONESHOT : 0);
+
+ HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), dispctrl);
/* When feeding the transposer block the pixelvalve is unneeded and
* should not be enabled.
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 649bf47c80e5..1e226454c9a6 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -332,7 +332,11 @@ struct vc4_hvs {
spinlock_t mm_lock;
struct drm_mm_node mitchell_netravali_filter;
+
struct debugfs_regset32 regset;
+
+ /* HVS version 5 flag, therefore requires updated dlist structures */
+ bool hvs5;
};
struct vc4_plane {
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 5a43659da319..0fe4758de03a 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -230,6 +230,9 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
hvs->pdev = pdev;
+ if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm2711-hvs"))
+ hvs->hvs5 = true;
+
hvs->regs = vc4_ioremap_regs(pdev, 0);
if (IS_ERR(hvs->regs))
return PTR_ERR(hvs->regs);
@@ -238,7 +241,10 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
hvs->regset.regs = hvs_regs;
hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
- hvs->dlist = hvs->regs + SCALER_DLIST_START;
+ if (!hvs->hvs5)
+ hvs->dlist = hvs->regs + SCALER_DLIST_START;
+ else
+ hvs->dlist = hvs->regs + SCALER5_DLIST_START;
spin_lock_init(&hvs->mm_lock);
@@ -256,7 +262,12 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
* between planes when they don't overlap on the screen, but
* for now we just allocate globally.
*/
- drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
+ if (!hvs->hvs5)
+ /* 96kB */
+ drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
+ else
+ /* 70k words */
+ drm_mm_init(&hvs->lbm_mm, 0, 70 * 2 * 1024);
/* Upload filter kernels. We only have the one for now, so we
* keep it around for the lifetime of the driver.
@@ -341,6 +352,7 @@ static int vc4_hvs_dev_remove(struct platform_device *pdev)
}
static const struct of_device_id vc4_hvs_dt_match[] = {
+ { .compatible = "brcm,bcm2711-hvs" },
{ .compatible = "brcm,bcm2835-hvs" },
{}
};
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 57a73a2e2e5c..1575c05e3106 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -32,45 +32,60 @@ static const struct hvs_format {
u32 drm; /* DRM_FORMAT_* */
u32 hvs; /* HVS_FORMAT_* */
u32 pixel_order;
+ u32 pixel_order_hvs5;
} hvs_formats[] = {
{
- .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_XRGB8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
},
{
- .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_ARGB8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
},
{
- .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_ABGR8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ARGB,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_XBGR8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ARGB,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
+ .drm = DRM_FORMAT_RGB565,
+ .hvs = HVS_PIXEL_FORMAT_RGB565,
.pixel_order = HVS_PIXEL_ORDER_XRGB,
},
{
- .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
+ .drm = DRM_FORMAT_BGR565,
+ .hvs = HVS_PIXEL_FORMAT_RGB565,
.pixel_order = HVS_PIXEL_ORDER_XBGR,
},
{
- .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
+ .drm = DRM_FORMAT_ARGB1555,
+ .hvs = HVS_PIXEL_FORMAT_RGBA5551,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
+ .drm = DRM_FORMAT_XRGB1555,
+ .hvs = HVS_PIXEL_FORMAT_RGBA5551,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
+ .drm = DRM_FORMAT_RGB888,
+ .hvs = HVS_PIXEL_FORMAT_RGB888,
.pixel_order = HVS_PIXEL_ORDER_XRGB,
},
{
- .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
+ .drm = DRM_FORMAT_BGR888,
+ .hvs = HVS_PIXEL_FORMAT_RGB888,
.pixel_order = HVS_PIXEL_ORDER_XBGR,
},
{
@@ -781,35 +796,6 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
return -EINVAL;
}
- /* Control word */
- vc4_dlist_write(vc4_state,
- SCALER_CTL0_VALID |
- (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
- (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
- VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
- (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
- (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
- VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
- (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
- VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
- VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
-
- /* Position Word 0: Image Positions and Alpha Value */
- vc4_state->pos0_offset = vc4_state->dlist_count;
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
- VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
- VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
-
- /* Position Word 1: Scaled Image Dimensions. */
- if (!vc4_state->is_unity) {
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(vc4_state->crtc_w,
- SCALER_POS1_SCL_WIDTH) |
- VC4_SET_FIELD(vc4_state->crtc_h,
- SCALER_POS1_SCL_HEIGHT));
- }
-
/* Don't waste cycles mixing with plane alpha if the set alpha
* is opaque or there is no per-pixel alpha information.
* In any case we use the alpha property value as the fixed alpha.
@@ -817,20 +803,120 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
fb->format->has_alpha;
- /* Position Word 2: Source Image Size, Alpha */
- vc4_state->pos2_offset = vc4_state->dlist_count;
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(fb->format->has_alpha ?
- SCALER_POS2_ALPHA_MODE_PIPELINE :
- SCALER_POS2_ALPHA_MODE_FIXED,
- SCALER_POS2_ALPHA_MODE) |
- (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
- (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
- VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
- VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
+ if (!vc4->hvs->hvs5) {
+ /* Control word */
+ vc4_dlist_write(vc4_state,
+ SCALER_CTL0_VALID |
+ (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
+ (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
+ VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
+ (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
+ (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
+ VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
+ (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
+ VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
+ VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
+
+ /* Position Word 0: Image Positions and Alpha Value */
+ vc4_state->pos0_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
+ VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
+ VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
+
+ /* Position Word 1: Scaled Image Dimensions. */
+ if (!vc4_state->is_unity) {
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->crtc_w,
+ SCALER_POS1_SCL_WIDTH) |
+ VC4_SET_FIELD(vc4_state->crtc_h,
+ SCALER_POS1_SCL_HEIGHT));
+ }
+
+ /* Position Word 2: Source Image Size, Alpha */
+ vc4_state->pos2_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(fb->format->has_alpha ?
+ SCALER_POS2_ALPHA_MODE_PIPELINE :
+ SCALER_POS2_ALPHA_MODE_FIXED,
+ SCALER_POS2_ALPHA_MODE) |
+ (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
+ (fb->format->has_alpha ?
+ SCALER_POS2_ALPHA_PREMULT : 0) |
+ VC4_SET_FIELD(vc4_state->src_w[0],
+ SCALER_POS2_WIDTH) |
+ VC4_SET_FIELD(vc4_state->src_h[0],
+ SCALER_POS2_HEIGHT));
+
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+
+ } else {
+ u32 hvs_pixel_order = format->pixel_order;
- /* Position Word 3: Context. Written by the HVS. */
- vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+ if (format->pixel_order_hvs5)
+ hvs_pixel_order = format->pixel_order_hvs5;
+
+ /* Control word */
+ vc4_dlist_write(vc4_state,
+ SCALER_CTL0_VALID |
+ (hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
+ (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
+ VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
+ (vc4_state->is_unity ?
+ SCALER5_CTL0_UNITY : 0) |
+ VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
+ VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
+ SCALER5_CTL0_ALPHA_EXPAND |
+ SCALER5_CTL0_RGB_EXPAND);
+
+ /* Position Word 0: Image Positions and Alpha Value */
+ vc4_state->pos0_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ (rotation & DRM_MODE_REFLECT_Y ?
+ SCALER5_POS0_VFLIP : 0) |
+ VC4_SET_FIELD(vc4_state->crtc_x,
+ SCALER_POS0_START_X) |
+ (rotation & DRM_MODE_REFLECT_X ?
+ SCALER5_POS0_HFLIP : 0) |
+ VC4_SET_FIELD(vc4_state->crtc_y,
+ SCALER5_POS0_START_Y)
+ );
+
+ /* Control Word 2 */
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(state->alpha >> 4,
+ SCALER5_CTL2_ALPHA) |
+ fb->format->has_alpha ?
+ SCALER5_CTL2_ALPHA_PREMULT : 0 |
+ (mix_plane_alpha ?
+ SCALER5_CTL2_ALPHA_MIX : 0) |
+ VC4_SET_FIELD(fb->format->has_alpha ?
+ SCALER5_CTL2_ALPHA_MODE_PIPELINE :
+ SCALER5_CTL2_ALPHA_MODE_FIXED,
+ SCALER5_CTL2_ALPHA_MODE)
+ );
+
+ /* Position Word 1: Scaled Image Dimensions. */
+ if (!vc4_state->is_unity) {
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->crtc_w,
+ SCALER_POS1_SCL_WIDTH) |
+ VC4_SET_FIELD(vc4_state->crtc_h,
+ SCALER_POS1_SCL_HEIGHT));
+ }
+
+ /* Position Word 2: Source Image Size */
+ vc4_state->pos2_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->src_w[0],
+ SCALER5_POS2_WIDTH) |
+ VC4_SET_FIELD(vc4_state->src_h[0],
+ SCALER5_POS2_HEIGHT));
+
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+ }
/* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
@@ -1208,6 +1294,10 @@ static bool vc4_format_mod_supported(struct drm_plane *plane,
default:
return false;
}
+ case DRM_FORMAT_RGBX1010102:
+ case DRM_FORMAT_BGRX1010102:
+ case DRM_FORMAT_RGBA1010102:
+ case DRM_FORMAT_BGRA1010102:
case DRM_FORMAT_YUV422:
case DRM_FORMAT_YVU422:
case DRM_FORMAT_YUV420:
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index b5a6b4cdd332..8a51baf681fe 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -328,6 +328,20 @@
# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
+# define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)
+# define SCALER5_DISPCTRLX_WIDTH_SHIFT 16
+/* Generates a single frame when VSTART is seen and stops at the last
+ * pixel read from the FIFO.
+ */
+# define SCALER5_DISPCTRLX_ONESHOT BIT(15)
+/* Processes a single context in the dlist and then task switch,
+ * instead of an entire line.
+ */
+# define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)
+# define SCALER5_DISPCTRLX_ONECTX_SHIFT 13
+# define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)
+# define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0
+
#define SCALER_DISPBKGND0 0x00000044
# define SCALER_DISPBKGND_AUTOHS BIT(31)
# define SCALER_DISPBKGND_INTERLACE BIT(30)
@@ -461,6 +475,8 @@
#define SCALER_DLIST_START 0x00002000
#define SCALER_DLIST_SIZE 0x00004000
+#define SCALER5_DLIST_START 0x00004000
+
#define VC4_HDMI_CORE_REV 0x000
#define VC4_HDMI_SW_RESET_CONTROL 0x004
@@ -826,6 +842,8 @@ enum hvs_pixel_format {
HVS_PIXEL_FORMAT_PALETTE = 13,
HVS_PIXEL_FORMAT_YUV444_RGB = 14,
HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
+ HVS_PIXEL_FORMAT_RGBA1010102 = 16,
+ HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,
};
/* Note: the LSB is the rightmost character shown. Only valid for
@@ -880,6 +898,10 @@ enum hvs_pixel_format {
#define SCALER_CTL0_RGBA_EXPAND_MSB 2
#define SCALER_CTL0_RGBA_EXPAND_ROUND 3
+#define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
+
+#define SCALER5_CTL0_RGB_EXPAND BIT(11)
+
#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
#define SCALER_CTL0_SCL1_SHIFT 8
@@ -897,10 +919,13 @@ enum hvs_pixel_format {
/* Set to indicate no scaling. */
#define SCALER_CTL0_UNITY BIT(4)
+#define SCALER5_CTL0_UNITY BIT(15)
#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
#define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
+#define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
+
#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
#define SCALER_POS0_FIXED_ALPHA_SHIFT 24
@@ -910,12 +935,48 @@ enum hvs_pixel_format {
#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
#define SCALER_POS0_START_X_SHIFT 0
+#define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)
+#define SCALER5_POS0_START_Y_SHIFT 16
+
+#define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)
+#define SCALER5_POS0_START_X_SHIFT 0
+
+#define SCALER5_POS0_VFLIP BIT(31)
+#define SCALER5_POS0_HFLIP BIT(15)
+
+#define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
+#define SCALER5_CTL2_ALPHA_MODE_SHIFT 30
+#define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0
+#define SCALER5_CTL2_ALPHA_MODE_FIXED 1
+#define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO 2
+#define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3
+
+#define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
+
+#define SCALER5_CTL2_ALPHA_MIX BIT(28)
+
+#define SCALER5_CTL2_ALPHA_LOC BIT(25)
+
+#define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17)
+#define SCALER5_CTL2_MAP_SEL_SHIFT 17
+
+#define SCALER5_CTL2_GAMMA BIT(16)
+
+#define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)
+#define SCALER5_CTL2_ALPHA_SHIFT 4
+
#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
#define SCALER_POS1_SCL_HEIGHT_SHIFT 16
#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
#define SCALER_POS1_SCL_WIDTH_SHIFT 0
+#define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)
+#define SCALER5_POS1_SCL_HEIGHT_SHIFT 16
+
+#define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
+#define SCALER5_POS1_SCL_WIDTH_SHIFT 0
+
#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
#define SCALER_POS2_ALPHA_MODE_SHIFT 30
#define SCALER_POS2_ALPHA_MODE_PIPELINE 0
@@ -931,6 +992,12 @@ enum hvs_pixel_format {
#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
#define SCALER_POS2_WIDTH_SHIFT 0
+#define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)
+#define SCALER5_POS2_HEIGHT_SHIFT 16
+
+#define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)
+#define SCALER5_POS2_WIDTH_SHIFT 0
+
/* Color Space Conversion words. Some values are S2.8 signed
* integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
* 0x2: 2, 0x3: -1}
--
git-series 0.9.1
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next prev parent reply other threads:[~2020-05-28 7:44 UTC|newest]
Thread overview: 151+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-27 15:47 [PATCH v3 000/105] drm/vc4: Support BCM2711 Display Pipeline Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 001/105] reset: Move reset-simple header out of drivers/reset Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 002/105] reset: simple: Add reset callback Maxime Ripard
2020-05-27 16:03 ` Philipp Zabel
2020-05-27 15:47 ` [PATCH v3 003/105] dt-bindings: clock: Add BCM2711 DVP binding Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 004/105] clk: bcm: Add BCM2711 DVP driver Maxime Ripard
2020-06-04 17:26 ` Nicolas Saenz Julienne
2020-06-05 17:43 ` Maxime Ripard
2020-06-05 18:11 ` Nicolas Saenz Julienne
2020-06-05 17:56 ` Eric Anholt
2020-05-27 15:47 ` [PATCH v3 005/105] ARM: dts: bcm2711: Add HDMI DVP Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 006/105] dt-bindings: display: Convert VC4 bindings to schemas Maxime Ripard
2020-05-27 19:12 ` Rob Herring
2020-06-02 15:00 ` Maxime Ripard
2020-06-17 20:21 ` Rob Herring
2020-05-27 15:47 ` [PATCH v3 007/105] dt-bindings: display: vc4: dpi: Add missing clock-names property Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 008/105] dt-bindings: display: vc4: dsi: Add missing clock properties Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 009/105] dt-bindings: display: vc4: hdmi: Add missing clock-names property Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 010/105] dt-bindings: display: vc4: Document BCM2711 VC5 Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 011/105] drm/vc4: drv: Add include guards Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 012/105] drm/vc4: drv: Support BCM2711 Maxime Ripard
2020-05-27 16:27 ` Eric Anholt
2020-05-27 15:47 ` [PATCH v3 013/105] dt-bindings: display: Add support for the BCM2711 HVS Maxime Ripard
2020-05-27 15:47 ` Maxime Ripard [this message]
2020-05-27 15:47 ` [PATCH v3 015/105] drm/vc4: hvs: Boost the core clock during modeset Maxime Ripard
2020-05-27 16:33 ` Eric Anholt
2020-06-02 12:52 ` Maxime Ripard
2020-06-02 17:52 ` Eric Anholt
2020-05-27 15:47 ` [PATCH v3 016/105] drm/vc4: plane: Improve LBM usage Maxime Ripard
2020-05-27 16:44 ` Eric Anholt
2020-05-27 15:47 ` [PATCH v3 017/105] drm/vc4: plane: Move planes creation to its own function Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 018/105] drm/vc4: plane: Move additional planes creation to driver Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 019/105] drm/vc4: plane: Register all the planes at once Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 020/105] drm/vc4: plane: Create overlays for any CRTC Maxime Ripard
2020-05-27 16:52 ` Eric Anholt
2020-05-27 15:47 ` [PATCH v3 021/105] drm/vc4: plane: Create more planes Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 022/105] drm/vc4: crtc: Rename SoC data structures Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 023/105] drm/vc4: crtc: Switch to of_device_get_match_data Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 024/105] drm/vc4: crtc: Move crtc state to common header Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 025/105] drm/vc4: crtc: Deal with different number of pixel per clock Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 026/105] drm/vc4: crtc: Use a shared interrupt Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 027/105] drm/vc4: crtc: Turn static const variable into a define Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 028/105] drm/vc4: crtc: Restrict HACT_ACT setup to DSI Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 029/105] drm/vc4: crtc: Move the cob allocation outside of bind Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 030/105] drm/vc4: crtc: Rename HVS channel to output Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 031/105] drm/vc4: crtc: Use local chan variable Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 032/105] drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable Maxime Ripard
2020-05-27 16:54 ` Eric Anholt
2020-06-02 14:12 ` Maxime Ripard
2020-06-02 15:02 ` Dave Stevenson
2020-06-02 19:31 ` Eric Anholt
2020-06-02 20:03 ` Stefan Wahren
2020-06-03 13:14 ` Maxime Ripard
2020-06-03 15:26 ` Stefan Wahren
2020-06-12 15:35 ` Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 033/105] drm/vc4: crtc: Assign output to channel automatically Maxime Ripard
2020-05-27 17:23 ` Eric Anholt
2020-06-16 15:04 ` Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 034/105] drm/vc4: crtc: Add FIFO depth to vc4_crtc_data Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 035/105] drm/vc4: crtc: Add function to compute FIFO level bits Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 036/105] drm/vc4: crtc: Rename HDMI encoder type to HDMI0 Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 037/105] drm/vc4: crtc: Add HDMI1 encoder type Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 038/105] drm/vc4: crtc: Remove redundant call to drm_crtc_enable_color_mgmt Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 039/105] drm/vc4: crtc: Disable color management for HVS5 Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 040/105] drm/vc4: crtc: Turn pixelvalve reset into a function Maxime Ripard
2020-05-27 17:30 ` Eric Anholt
2020-05-27 15:48 ` [PATCH v3 041/105] drm/vc4: crtc: Move HVS mode config to HVS file Maxime Ripard
2020-05-27 18:26 ` Eric Anholt
2020-05-27 15:48 ` [PATCH v3 042/105] drm/vc4: crtc: Move PV dump to config_pv Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 043/105] drm/vc4: crtc: Move HVS init and close to a function Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 044/105] drm/vc4: crtc: Move the HVS gamma LUT setup to our init function Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 045/105] drm/vc4: hvs: Make sure our channel is reset Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 046/105] drm/vc4: hvs: Remove mode_set_nofb Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 047/105] drm/vc4: crtc: " Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 048/105] drm/vc4: crtc: Remove redundant pixelvalve reset Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 049/105] drm/vc4: crtc: Move HVS channel init before the PV initialisation Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 050/105] drm/vc4: encoder: Add finer-grained encoder callbacks Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 051/105] drm/vc4: crtc: Add a delay after disabling the PixelValve output Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 052/105] drm/vc4: crtc: Clear the PixelValve FIFO on disable Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 053/105] drm/vc4: crtc: Clear the PixelValve FIFO during configuration Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 054/105] drm/vc4: hvs: Make the stop_channel function public Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 055/105] drm/vc4: hvs: Introduce a function to get the assigned FIFO Maxime Ripard
2020-05-27 19:40 ` Eric Anholt
2020-06-03 9:43 ` Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 056/105] drm/vc4: crtc: Move the CRTC disable out Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 057/105] drm/vc4: drv: Disable the CRTC at boot time Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 058/105] dt-bindings: display: vc4: pv: Add BCM2711 pixel valves Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 059/105] drm/vc4: crtc: Add BCM2711 pixelvalves Maxime Ripard
2020-05-27 19:24 ` Eric Anholt
2020-05-27 15:48 ` [PATCH v3 060/105] drm/vc4: crtc: Make state functions public Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 061/105] drm/vc4: crtc: Split CRTC data in two Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 062/105] drm/vc4: crtc: Only access the PixelValve registers if we have to Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 063/105] drm/vc4: crtc: Move the CRTC initialisation to a separate function Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 064/105] drm/vc4: crtc: Change the HVS5 test for of_device_is_compatible Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 065/105] drm/vc4: crtc: Move the txp_armed function to the TXP Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 066/105] drm/vc4: txp: Turn the TXP into a CRTC of its own Maxime Ripard
2020-05-28 15:51 ` Emil Velikov
2020-06-10 18:40 ` Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 067/105] drm/vc4: crtc: Remove the feed_txp tests Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 068/105] drm/vc4: hdmi: Use debugfs private field Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 069/105] drm/vc4: hdmi: Move structure to header Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 070/105] drm/vc4: hdmi: rework connectors and encoders Maxime Ripard
2020-05-27 18:41 ` Eric Anholt
2020-06-02 15:54 ` Maxime Ripard
2020-06-03 17:32 ` Stefan Wahren
2020-06-05 14:35 ` Maxime Ripard
2020-06-06 8:06 ` Stefan Wahren
2020-06-11 13:34 ` Maxime Ripard
2020-06-14 16:16 ` Stefan Wahren
2020-06-16 12:30 ` Maxime Ripard
2020-06-16 19:09 ` Stefan Wahren
2020-05-27 15:48 ` [PATCH v3 071/105] drm/vc4: hdmi: Remove DDC argument to connector_init Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 072/105] drm/vc4: hdmi: Rename hdmi to vc4_hdmi Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 073/105] drm/vc4: hdmi: Move accessors " Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 074/105] drm/vc4: hdmi: Use local vc4_hdmi directly Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 075/105] drm/vc4: hdmi: Add container_of macros for encoders and connectors Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 076/105] drm/vc4: hdmi: Pass vc4_hdmi to CEC code Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 077/105] drm/vc4: hdmi: Remove vc4_dev hdmi pointer Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 078/105] drm/vc4: hdmi: Remove vc4_hdmi_connector Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 079/105] drm/vc4: hdmi: Introduce resource init and variant Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 080/105] drm/vc4: hdmi: Implement a register layout abstraction Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 081/105] drm/vc4: hdmi: Add reset callback Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 082/105] drm/vc4: hdmi: Add PHY init and disable function Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 083/105] drm/vc4: hdmi: Add PHY RNG enable / " Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 084/105] drm/vc4: hdmi: Add a CSC setup callback Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 085/105] drm/vc4: hdmi: Store the encoder type in the variant structure Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 086/105] drm/vc4: hdmi: Deal with multiple debugfs files Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 087/105] drm/vc4: hdmi: Move CEC init to its own function Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 088/105] drm/vc4: hdmi: Add CEC support flag Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 089/105] drm/vc4: hdmi: Remove unused CEC_CLOCK_DIV define Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 090/105] drm/vc4: hdmi: Rename drm_encoder pointer in mode_valid Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 091/105] drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 092/105] drm/vc4: hdmi: Use clk_set_min_rate instead Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 093/105] drm/vc4: hdmi: Use reg-names to retrieve the HDMI audio registers Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 094/105] drm/vc4: hdmi: Reset audio infoframe on encoder_enable if previously streaming Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 095/105] drm/vc4: hdmi: Set the b-frame marker to the match ALSA's default Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 096/105] drm/vc4: hdmi: Add audio-related callbacks Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 097/105] drm/vc4: hdmi: Deal with multiple ALSA cards Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 098/105] drm/vc4: hdmi: Remove register dumps in enable Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 099/105] drm/vc4: hdmi: Always recenter the HDMI FIFO Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 100/105] drm/vc4: hdmi: Implement finer-grained hooks Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 101/105] drm/vc4: hdmi: Do the VID_CTL configuration at once Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 102/105] drm/vc4: hdmi: Switch to blank pixels when disabled Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 103/105] drm/vc4: hdmi: Support the BCM2711 HDMI controllers Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 104/105] dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings Maxime Ripard
2020-05-29 18:18 ` Rob Herring
2020-06-02 15:08 ` Maxime Ripard
2020-06-08 23:01 ` Rob Herring
2020-05-27 15:49 ` [PATCH v3 105/105] ARM: dts: bcm2711: Enable the display pipeline Maxime Ripard
2020-06-03 20:11 ` Stefan Wahren
2020-06-02 20:12 ` [PATCH v3 000/105] drm/vc4: Support BCM2711 Display Pipeline Stefan Wahren
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