From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 24 Oct 2019 14:08:41 -0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iNdn6-000066-GB for speck@linutronix.de; Thu, 24 Oct 2019 16:08:41 +0200 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id F3A57B238 for ; Thu, 24 Oct 2019 14:08:33 +0000 (UTC) Date: Thu, 24 Oct 2019 16:08:21 +0200 From: Borislav Petkov Subject: [MODERATED] Re: [PATCH v7 00/10] TAAv7 0 Message-ID: <20191024140821.GA14115@zn.tnic> References: <20191023154604.GO12272@zn.tnic> <20191023221214.GA26994@guptapadev.amr> MIME-Version: 1.0 In-Reply-To: <20191023221214.GA26994@guptapadev.amr> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: speck@linutronix.de List-ID: On Wed, Oct 23, 2019 at 03:12:14PM -0700, speck for Pawan Gupta wrote: > Below are the CPUs with MDS_NO=3D1. > +----------------------------+------------------+------------+ > | Name | Family / model | Stepping | > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D+ > | Whiskey Lake (ULT refresh) | 06_8E | 0xC | > +----------------------------+------------------+------------+ > | 2nd gen Cascade Lake | 06_55 | 6, 7 | Ok, found one of this type: vendor_id : GenuineIntel cpu family : 6 model : 85 model name : Intel(R) Xeon(R) Platinum 8260L CPU @ 2.40GHz stepping : 6 microcode got updated to: [ 0.000000] microcode: microcode updated early to revision 0x400002c, date= =3D 2019-09-05 and ARCH_CAP MSR is: MSR_0x10A =3D 0xab =3D 1010_1011 Booting with CONFIG_X86_INTEL_TSX_MODE_OFF=3Dy gives: [ 0.316520] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user p= ointer sanitization [ 0.316522] Spectre V2 : Mitigation: Enhanced IBRS [ 0.316523] Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB o= n context switch [ 0.316525] Spectre V2 : mitigation: Enabling conditional Indirect Branch = Prediction Barrier [ 0.316527] Speculative Store Bypass: Mitigation: Speculative Store Bypass= disabled via prctl and seccomp [ 0.316528] TAA: Mitigation: TSX disabled Booting with tsx=3Don gives [ 0.314958] TAA: Mitigation: Clear CPU buffers and with tsx=3Don tsx_async_abort=3Dfull,nosmt [ 0.315439] SMT: disabled [ 0.315440] TAA: Mitigation: Clear CPU buffers I think we're good to go... --=20 Regards/Gruss, Boris. SUSE Software Solutions Germany GmbH, GF: Felix Imend=C3=B6rffer, HRB 36809, = AG N=C3=BCrnberg --=20