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From: mark gross <mgross@linux.intel.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: ***UNCHECKED*** Re: Re: [PATCH v7 3/5] NX 3
Date: Tue, 29 Oct 2019 13:33:53 -0700	[thread overview]
Message-ID: <20191029203353.GA10372@u1904> (raw)
In-Reply-To: <801f92a4-befa-79da-8f64-7d721f6e5c8f@redhat.com>

On Fri, Oct 25, 2019 at 12:39:58PM +0200, speck for Paolo Bonzini wrote:
> On 25/10/19 11:45, speck for Joerg Roedel wrote:
> > On Fri, Oct 25, 2019 at 11:08:25AM +0200, speck for Paolo Bonzini wrote:
> >> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> >> index e7970a2e8eae..8979d5e7b6f5 100644
> >> --- a/arch/x86/kvm/vmx/vmx.c
> >> +++ b/arch/x86/kvm/vmx/vmx.c
> >> @@ -969,17 +969,9 @@ static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
> >>  	u64 guest_efer = vmx->vcpu.arch.efer;
> >>  	u64 ignore_bits = 0;
> >>  
> >> -	if (!enable_ept) {
> >> -		/*
> >> -		 * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
> >> -		 * host CPUID is more efficient than testing guest CPUID
> >> -		 * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
> >> -		 */
> >> -		if (boot_cpu_has(X86_FEATURE_SMEP))
> >> -			guest_efer |= EFER_NX;
> >> -		else if (!(guest_efer & EFER_NX))
> >> -			ignore_bits |= EFER_NX;
> >> -	}
> >> +	/* Shadow paging assumes the NX bit to be available.  */
> >> +	if (!enable_ept)
> >> +		guest_efer |= EFER_NX;
> >>  
> >>  	/*
> >>  	 * LMA and LME handled by hardware; SCE meaningless outside long mode.
> > 
> > Works with ept on and off, thanks.
> 
> Thanks, I'll include also the AMD version in a new patch and send it out as v8:
> 
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index 4153ca8cddb7..29feb3ecc91c 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -739,8 +739,12 @@ static int get_npt_level(struct kvm_vcpu *vcpu)
>  static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
>  {
>  	vcpu->arch.efer = efer;
> -	if (!npt_enabled && !(efer & EFER_LMA))
> -		efer &= ~EFER_LME;
> +	if (!npt_enabled) {
> +		/* Shadow paging assumes the NX bit to be available.  */
> +		efer |= EFER_NXE;
                         ^EFER_NX ?
--mark

> +		if (!(efer & EFER_LMA))
> +			efer &= ~EFER_LME;
> +	}
>  
>  	to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
>  	mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
> 
> Paolo
> 

  reply	other threads:[~2019-10-29 20:33 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-24 16:34 [MODERATED] [PATCH v7 0/5] NX 0 Paolo Bonzini
2019-10-24 16:34 ` [MODERATED] [PATCH v7 1/5] NX 1 Paolo Bonzini
2019-10-30 18:38   ` [MODERATED] " Josh Poimboeuf
2019-10-31 11:05     ` Paolo Bonzini
2019-10-24 16:34 ` [MODERATED] [PATCH v7 2/5] NX 2 Paolo Bonzini
2019-10-24 16:34 ` [MODERATED] [PATCH v7 3/5] NX 3 Paolo Bonzini
2019-10-25  8:37   ` [MODERATED] Re: ***UNCHECKED*** " Joerg Roedel
2019-10-25  8:48     ` Paolo Bonzini
2019-10-25  9:03       ` [MODERATED] Re: ***UNCHECKED*** " Joerg Roedel
2019-10-25  9:08         ` Paolo Bonzini
2019-10-25  9:45           ` [MODERATED] Re: ***UNCHECKED*** " Joerg Roedel
2019-10-25 10:39             ` Paolo Bonzini
2019-10-29 20:33               ` mark gross [this message]
2019-10-31 11:02                 ` Paolo Bonzini
2019-10-24 16:34 ` [MODERATED] [PATCH v7 4/5] NX 4 Paolo Bonzini
2019-10-24 16:34 ` [MODERATED] [PATCH v7 5/5] NX 5 Paolo Bonzini
2019-10-24 18:27 ` [MODERATED] Re: [PATCH v7 0/5] NX 0 Ben Hutchings
2019-10-24 18:56   ` Paolo Bonzini

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