From: Andy Lutomirski <luto@amacapital.net>
To: speck@linutronix.de
Subject: [MODERATED] Re: [PATCH v5 04/11] TAAv5 4
Date: Sat, 5 Oct 2019 14:45:36 -0700 [thread overview]
Message-ID: <ad6be1a9-fad2-f0c9-957c-97208c97d790@amacapital.net> (raw)
In-Reply-To: <5d9839a4.1c69fb81.238e9.8312SMTPIN_ADDED_BROKEN@mx.google.com>
[-- Attachment #1: Type: text/plain, Size: 4518 bytes --]
On 10/4/19 11:29 PM, speck for Pawan Gupta wrote:
> Add kernel cmdline parameter "tsx" to control the Transactional
> Synchronization Extensions (TSX) feature. On CPUs that support TSX
> control, use "tsx=on|off" to enable or disable TSX. Not specifying this
> option is equivalent to "tsx=off".
>
> Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
> Reviewed-by: Mark Gross <mgross@linux.intel.com>
> Reviewed-by: Tony Luck <tony.luck@intel.com>
> Tested-by: Neelima Krishnan <neelima.krishnan@intel.com>
> ---
> .../admin-guide/kernel-parameters.txt | 11 +++
> arch/x86/kernel/cpu/tsx.c | 97 ++++++++++++++++---
> 2 files changed, 95 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
> index 4c1971960afa..832537d59562 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parameters.txt
> @@ -4813,6 +4813,17 @@
> interruptions from clocksource watchdog are not
> acceptable).
>
> + tsx= [X86] Control Transactional Synchronization
> + Extensions (TSX) feature in Intel processors that
> + support TSX control.
> +
> + This parameter controls the TSX feature. The options are:
> +
> + on - Enable TSX on the system.
> + off - Disable TSX on the system.
> +
> + Not specifying this option is equivalent to tsx=off.
> +
> turbografx.map[2|3]= [HW,JOY]
> TurboGraFX parallel port interface
> Format:
> diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c
> index c549750dd7c8..1c0cee7a7d46 100644
> --- a/arch/x86/kernel/cpu/tsx.c
> +++ b/arch/x86/kernel/cpu/tsx.c
> @@ -19,6 +19,30 @@ static enum tsx_ctrl_states {
> TSX_CTRL_NOT_SUPPORTED,
> } tsx_ctrl_state = TSX_CTRL_NOT_SUPPORTED;
>
> +static enum tsx_user_cmds {
> + TSX_USER_CMD_NONE,
> + TSX_USER_CMD_ON,
> + TSX_USER_CMD_OFF,
> +} tsx_user_cmd = TSX_USER_CMD_NONE;
> +
> +static int __init tsx_cmdline(char *str)
> +{
> + if (!str)
> + return -EINVAL;
> +
> + /*
> + * tsx_en/disable() are only called when
> + * X86_FEATURE_RTM and TSX_CTRL MSR are supported.
> + */
> + if (!strcmp(str, "on"))
> + tsx_user_cmd = TSX_USER_CMD_ON;
> + else if (!strcmp(str, "off"))
> + tsx_user_cmd = TSX_USER_CMD_OFF;
> +
> + return 0;
> +}
> +early_param("tsx", tsx_cmdline);
> +
> static void tsx_disable(void)
> {
> u64 tsx;
> @@ -38,6 +62,24 @@ static void tsx_disable(void)
> wrmsrl(MSR_IA32_TSX_CTRL, tsx);
> }
>
> +static void tsx_enable(void)
> +{
> + u64 tsx;
> +
> + rdmsrl(MSR_IA32_TSX_CTRL, tsx);
> +
> + /* Enable the RTM feature in the cpu */
> + tsx &= ~TSX_CTRL_RTM_DISABLE;
> + /*
> + * Ensure TSX support is enumerated in CPUID.
> + * This is visible to userspace and will ensure they
> + * can enumerate and use the TSX feature.
> + */
> + tsx &= ~TSX_CTRL_CPUID_CLEAR;
> +
> + wrmsrl(MSR_IA32_TSX_CTRL, tsx);
> +}
> +
> static bool tsx_ctrl_is_supported(void)
> {
> u64 ia32_cap = read_ia32_arch_cap();
> @@ -55,18 +97,47 @@ void tsx_init(struct cpuinfo_x86 *c)
> if (!tsx_ctrl_is_supported())
> return;
>
> - /*
> - * Default to TSX_CTRL_DISABLE. This is because on certain processors
> - * TSX may be used as part of a speculative side channel attack.
> - */
> - tsx_ctrl_state = TSX_CTRL_DISABLE;
> + switch (tsx_user_cmd) {
> + case TSX_USER_CMD_ON:
> + tsx_ctrl_state = TSX_CTRL_ENABLE;
> + break;
> + case TSX_USER_CMD_OFF:
> + tsx_ctrl_state = TSX_CTRL_DISABLE;
> + break;
> + case TSX_USER_CMD_NONE:
> + default:
> + /*
> + * If user provided an invalid option or tsx= is not provided
> + * on cmdline default to TSX_CTRL_DISABLE. This is because on
> + * certain processors TSX may be used as part of a speculative
> + * side channel attack.
> + */
> + tsx_ctrl_state = TSX_CTRL_DISABLE;
> + }
This code is bizarre. Why are you separating tsx_ctrl_state from
tsx_user_cmd? Just have one copy of this, please. You shouldn't be
writing to a *global* cpu state variable like this in a percpu init
function. This code should just program the MSR.
Also, the new improved just-one-enum-for-everything global variable
should be __ro_after_init.
Given that you are doing the percpu config for each cpu, setup_clear_...
should be unnecessary. It's just a helper that automatically clears the
bit for other CPUs.
next prev parent reply other threads:[~2019-10-05 21:45 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-05 6:17 [MODERATED] [PATCH v5 00/11] TAAv5 0 Pawan Gupta
2019-10-05 6:26 ` [MODERATED] [PATCH v5 01/11] TAAv5 1 Pawan Gupta
2019-10-05 6:27 ` [MODERATED] [PATCH v5 02/11] TAAv5 2 Pawan Gupta
2019-10-05 6:28 ` [MODERATED] [PATCH v5 03/11] TAAv5 3 Pawan Gupta
2019-10-05 6:29 ` [MODERATED] [PATCH v5 04/11] TAAv5 4 Pawan Gupta
2019-10-05 6:30 ` [MODERATED] [PATCH v5 05/11] TAAv5 5 Pawan Gupta
2019-10-05 6:31 ` [MODERATED] [PATCH v5 06/11] TAAv5 6 Pawan Gupta
2019-10-05 6:32 ` [MODERATED] [PATCH v5 07/11] TAAv5 7 Pawan Gupta
2019-10-05 6:33 ` [MODERATED] [PATCH v5 08/11] TAAv5 8 Pawan Gupta
2019-10-05 6:34 ` [MODERATED] [PATCH v5 09/11] TAAv5 9 Pawan Gupta
2019-10-05 6:35 ` [MODERATED] [PATCH v5 10/11] TAAv5 10 Pawan Gupta
2019-10-05 6:36 ` [MODERATED] [PATCH v5 11/11] TAAv5 11 Pawan Gupta
2019-10-05 10:54 ` [MODERATED] Re: [PATCH v5 02/11] TAAv5 2 Borislav Petkov
2019-10-07 17:48 ` Pawan Gupta
[not found] ` <5d98396a.1c69fb81.6c7a8.23b1SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-05 21:43 ` [MODERATED] Re: [PATCH v5 03/11] TAAv5 3 Andy Lutomirski
2019-10-07 17:50 ` Pawan Gupta
[not found] ` <5d9839a4.1c69fb81.238e9.8312SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-05 21:45 ` Andy Lutomirski [this message]
[not found] ` <5d983ad2.1c69fb81.63edd.6575SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-05 21:49 ` [MODERATED] Re: [PATCH v5 09/11] TAAv5 9 Andy Lutomirski
2019-10-07 18:35 ` Pawan Gupta
[not found] ` <5d9838f1.1c69fb81.f1bab.d886SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-05 21:49 ` [MODERATED] Re: [PATCH v5 01/11] TAAv5 1 Andy Lutomirski
2019-10-06 17:40 ` Andrew Cooper
[not found] ` <5d983ad2.1c69fb81.e6640.8f51SMTPIN_ADDED_BROKEN@mx.google.com>
2019-10-06 17:06 ` [MODERATED] Re: [PATCH v5 09/11] TAAv5 9 Greg KH
2019-10-08 6:01 ` Pawan Gupta
2019-10-10 21:31 ` Pawan Gupta
2019-10-11 8:45 ` Greg KH
2019-10-21 8:00 ` Thomas Gleixner
2019-10-08 2:46 ` [MODERATED] Re: [PATCH v5 05/11] TAAv5 5 Josh Poimboeuf
2019-10-09 1:45 ` Pawan Gupta
2019-10-08 2:57 ` [MODERATED] Re: [PATCH v5 09/11] TAAv5 9 Josh Poimboeuf
2019-10-08 6:10 ` Pawan Gupta
2019-10-08 10:49 ` Jiri Kosina
2019-10-09 13:12 ` [MODERATED] Re: ***UNCHECKED*** [PATCH v5 08/11] TAAv5 8 Michal Hocko
2019-10-14 19:41 ` Thomas Gleixner
2019-10-14 19:51 ` [MODERATED] " Jiri Kosina
2019-10-14 21:04 ` [MODERATED] " Borislav Petkov
2019-10-14 21:31 ` Jiri Kosina
2019-10-15 8:01 ` Thomas Gleixner
2019-10-15 10:34 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
2019-10-15 13:06 ` Josh Poimboeuf
2019-10-15 13:10 ` Jiri Kosina
2019-10-15 15:26 ` Josh Poimboeuf
2019-10-15 15:32 ` Jiri Kosina
2019-10-15 19:34 ` Tyler Hicks
2019-10-15 20:00 ` Josh Poimboeuf
2019-10-15 20:15 ` Jiri Kosina
2019-10-15 20:35 ` Jiri Kosina
2019-10-15 20:54 ` Josh Poimboeuf
2019-10-15 20:56 ` [MODERATED] " Pawan Gupta
2019-10-15 21:14 ` Jiri Kosina
2019-10-15 23:12 ` Josh Poimboeuf
2019-10-15 23:13 ` [MODERATED] [AUTOREPLY] [MODERATED] [AUTOREPLY] Automatic reply: " James, Hengameh M
2019-10-16 4:52 ` [MODERATED] " Jiri Kosina
2019-10-16 5:05 ` Jiri Kosina
2019-10-21 21:15 ` Luck, Tony
2019-10-16 7:14 ` Josh Poimboeuf
2019-10-16 7:20 ` Jiri Kosina
2019-10-18 1:17 ` Ben Hutchings
2019-10-18 4:04 ` Pawan Gupta
2019-10-15 17:47 ` Borislav Petkov
2019-10-16 7:26 ` [MODERATED] Re: ***UNCHECKED*** " Jiri Kosina
2019-10-16 7:54 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
2019-10-16 9:23 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
2019-10-16 12:15 ` Thomas Gleixner
2019-10-16 18:34 ` [MODERATED] " Pawan Gupta
2019-10-18 0:14 ` Pawan Gupta
2019-10-21 8:09 ` Thomas Gleixner
2019-10-21 12:54 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
2019-10-21 20:01 ` [MODERATED] " Pawan Gupta
2019-10-21 20:33 ` Josh Poimboeuf
2019-10-21 20:34 ` Josh Poimboeuf
2019-10-21 20:33 ` Pawan Gupta
2019-10-21 23:01 ` Andrew Cooper
2019-10-21 23:37 ` Luck, Tony
2019-10-21 23:39 ` Andrew Cooper
2019-10-14 21:05 ` [MODERATED] Re: ***UNCHECKED*** " Michal Hocko
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