From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: i915 next Date: Tue, 12 Apr 2011 21:31:28 +0100 Message-ID: <1302640318-23165-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 409469EFF4 for ; Tue, 12 Apr 2011 13:32:06 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is just the first batch of patches that look ready for testing and feedback. 1-9: Eric's modesetting refactor. This has met with unanimous approval. 10-14: Ben's rc6 fixes for Ironlake, and Jesse's module parameter for SNB. 15-22: Enabling LLC by default on SNB. There are a couple of new patches in there since Eric's posting to switch pwrite and mmap GTT to use the cached CPU domains, which may or may not be strictly necessary for earlier chipsets. 23: Cache GT fifo count. Short term performance gain for the ddx, but will probably be dropped in favour of Ben's GT read/write fixes. Hint, Ben, hint. 24-25: Some minor code refactoring 26-30: Pipelined fence fixes. Feedback welcome thanks, -Chris