From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 28/30] drm/i915: Pass the fence register number to be written
Date: Tue, 12 Apr 2011 21:31:56 +0100 [thread overview]
Message-ID: <1302640318-23165-29-git-send-email-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <1302640318-23165-1-git-send-email-chris@chris-wilson.co.uk>
This simplifies a later change where we want to successfully write (or
pipeline) the fence update prior to updating the bo.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 61 ++++++++++++++++++--------------------
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 30 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ad0c2b7..ca14a86 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2321,12 +2321,12 @@ i915_gpu_idle(struct drm_device *dev)
}
static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
- struct intel_ring_buffer *pipelined)
+ struct intel_ring_buffer *pipelined,
+ int reg)
{
struct drm_device *dev = obj->base.dev;
drm_i915_private_t *dev_priv = dev->dev_private;
u32 size = obj->gtt_space->size;
- int regnum = obj->fence_reg;
uint64_t val;
val = (uint64_t)((obj->gtt_offset + size - 4096) &
@@ -2346,24 +2346,24 @@ static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
intel_ring_emit(pipelined, MI_NOOP);
intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
- intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
+ intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + reg*8);
intel_ring_emit(pipelined, (u32)val);
- intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
+ intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + reg*8 + 4);
intel_ring_emit(pipelined, (u32)(val >> 32));
intel_ring_advance(pipelined);
} else
- I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
+ I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
return 0;
}
static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
- struct intel_ring_buffer *pipelined)
+ struct intel_ring_buffer *pipelined,
+ int reg)
{
struct drm_device *dev = obj->base.dev;
drm_i915_private_t *dev_priv = dev->dev_private;
u32 size = obj->gtt_space->size;
- int regnum = obj->fence_reg;
uint64_t val;
val = (uint64_t)((obj->gtt_offset + size - 4096) &
@@ -2381,25 +2381,25 @@ static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
intel_ring_emit(pipelined, MI_NOOP);
intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
- intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
+ intel_ring_emit(pipelined, FENCE_REG_965_0 + reg*8);
intel_ring_emit(pipelined, (u32)val);
- intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
+ intel_ring_emit(pipelined, FENCE_REG_965_0 + reg*8 + 4);
intel_ring_emit(pipelined, (u32)(val >> 32));
intel_ring_advance(pipelined);
} else
- I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
+ I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
return 0;
}
static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
- struct intel_ring_buffer *pipelined)
+ struct intel_ring_buffer *pipelined,
+ int reg)
{
struct drm_device *dev = obj->base.dev;
drm_i915_private_t *dev_priv = dev->dev_private;
u32 size = obj->gtt_space->size;
- u32 fence_reg, val, pitch_val;
- int tile_width;
+ int tile_width, val;
if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
(size & -size) != size ||
@@ -2413,22 +2413,17 @@ static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
else
tile_width = 512;
- /* Note: pitch better be a power of two tile widths */
- pitch_val = obj->stride / tile_width;
- pitch_val = ffs(pitch_val) - 1;
-
val = obj->gtt_offset;
if (obj->tiling_mode == I915_TILING_Y)
val |= 1 << I830_FENCE_TILING_Y_SHIFT;
val |= I915_FENCE_SIZE_BITS(size);
- val |= pitch_val << I830_FENCE_PITCH_SHIFT;
+ val |= I915_FENCE_PITCH_BITS(obj->stride / tile_width);
val |= I830_FENCE_REG_VALID;
- fence_reg = obj->fence_reg;
- if (fence_reg < 8)
- fence_reg = FENCE_REG_830_0 + fence_reg * 4;
+ if (reg < 8)
+ reg = FENCE_REG_830_0 + reg * 4;
else
- fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
+ reg = FENCE_REG_945_8 + (reg - 8) * 4;
if (pipelined) {
int ret = intel_ring_begin(pipelined, 4);
@@ -2437,22 +2432,22 @@ static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
intel_ring_emit(pipelined, MI_NOOP);
intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit(pipelined, fence_reg);
+ intel_ring_emit(pipelined, reg);
intel_ring_emit(pipelined, val);
intel_ring_advance(pipelined);
} else
- I915_WRITE(fence_reg, val);
+ I915_WRITE(reg, val);
return 0;
}
static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
- struct intel_ring_buffer *pipelined)
+ struct intel_ring_buffer *pipelined,
+ int reg)
{
struct drm_device *dev = obj->base.dev;
drm_i915_private_t *dev_priv = dev->dev_private;
u32 size = obj->gtt_space->size;
- int regnum = obj->fence_reg;
uint32_t val;
uint32_t pitch_val;
@@ -2480,11 +2475,11 @@ static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
intel_ring_emit(pipelined, MI_NOOP);
intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
+ intel_ring_emit(pipelined, FENCE_REG_830_0 + reg*4);
intel_ring_emit(pipelined, val);
intel_ring_advance(pipelined);
} else
- I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
+ I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
return 0;
}
@@ -2625,6 +2620,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_fence_reg *reg;
+ int regnum;
int ret;
/* XXX disable pipelining. There are bugs. Shocking. */
@@ -2720,19 +2716,20 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
update:
obj->tiling_changed = false;
+ regnum = reg - dev_priv->fence_regs;
switch (INTEL_INFO(dev)->gen) {
case 6:
- ret = sandybridge_write_fence_reg(obj, pipelined);
+ ret = sandybridge_write_fence_reg(obj, pipelined, regnum);
break;
case 5:
case 4:
- ret = i965_write_fence_reg(obj, pipelined);
+ ret = i965_write_fence_reg(obj, pipelined, regnum);
break;
case 3:
- ret = i915_write_fence_reg(obj, pipelined);
+ ret = i915_write_fence_reg(obj, pipelined, regnum);
break;
case 2:
- ret = i830_write_fence_reg(obj, pipelined);
+ ret = i830_write_fence_reg(obj, pipelined, regnum);
break;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f39ac3a..024e01f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -264,6 +264,7 @@
#define I915_FENCE_START_MASK 0x0ff00000
#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
+#define I915_FENCE_PITCH_BITS(stride) ((ffs(stride) - 1) << I830_FENCE_PITCH_SHIFT)
#define FENCE_REG_965_0 0x03000
#define I965_FENCE_PITCH_SHIFT 2
--
1.7.4.1
next prev parent reply other threads:[~2011-04-12 20:33 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-12 20:31 i915 next Chris Wilson
2011-04-12 20:31 ` [PATCH 01/30] drm/i915: Split the crtc_mode_set function along HAS_PCH_SPLIT() lines Chris Wilson
2011-04-12 20:31 ` [PATCH 02/30] drm/i915: Move the vblank pre/post modeset to the common crtc_mode_set Chris Wilson
2011-04-12 20:31 ` [PATCH 03/30] drm/i915: Remove the PCH paths from the pre-Ironlake crtc_mode_set() Chris Wilson
2011-04-12 20:31 ` [PATCH 04/30] drm/i915: Drop the eDP paths from the pre-Ironlake crtc_mode_set Chris Wilson
2011-04-12 20:31 ` [PATCH 05/30] drm/i915: Drop the remaining bit of Ironlake code from i9xx_crtc_mode_set() Chris Wilson
2011-04-12 20:31 ` [PATCH 06/30] drm/i915: Drop non-HAS_PCH_SPLIT() code from ironlake_crtc_mode_set() Chris Wilson
2011-04-12 20:31 ` [PATCH 07/30] drm/i915: Drop remaining pre-Ironlake " Chris Wilson
2011-04-12 20:31 ` [PATCH 08/30] drm/i915: Clean up leftover DPLL and LVDS register choice from pch split Chris Wilson
2011-04-12 20:31 ` [PATCH 09/30] drm/i915: Fold the DPLL limit defines into the structs that use them Chris Wilson
2011-04-12 20:31 ` [PATCH 10/30] drm/i915: fix ilk rc6 teardown locking Chris Wilson
2011-04-12 20:31 ` [PATCH 11/30] drm/1915: ringbuffer wait for idle function Chris Wilson
2011-04-12 20:31 ` [PATCH 12/30] drm/i915: fix rc6 initialization on Ironlake Chris Wilson
2011-04-12 20:31 ` [PATCH 13/30] drm/i915: re-enable rc6 for ironlake Chris Wilson
2011-04-12 20:31 ` [PATCH 14/30] drm/i915: use i915_enable_rc6 on SNB too Chris Wilson
2011-04-12 20:31 ` [PATCH 15/30] drm/i915: Rename agp_type to cache_level Chris Wilson
2011-04-13 15:57 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 16/30] drm/i915: Mark the cursor and the overlay as being part of the display planes Chris Wilson
2011-04-13 16:00 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 17/30] drm/i915: Do not clflush snooped objects Chris Wilson
2011-04-13 16:04 ` Daniel Vetter
2011-04-13 17:34 ` Chris Wilson
2011-04-13 20:47 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 18/30] drm/i915: Add an interface to dynamically change the cache level Chris Wilson
2011-04-13 18:59 ` Daniel Vetter
2011-04-13 19:21 ` Chris Wilson
2011-04-13 22:27 ` [PATCH 1/3] drm/i915: Introduce i915_gem_object_finish_gpu() Chris Wilson
2011-04-13 22:27 ` [PATCH 2/3] drm/i915: Introduce i915_gem_object_finish_gtt() Chris Wilson
2011-04-13 22:27 ` [PATCH 3/3] drm/i915: Add an interface to dynamically change the cache level Chris Wilson
2011-04-12 20:31 ` [PATCH 19/30] drm/i915: Use the uncached domain for the display planes v2 Chris Wilson
2011-04-12 20:31 ` [PATCH 20/30] drm/i915: Use the CPU domain for snooped pwrites Chris Wilson
2011-04-12 20:31 ` [PATCH 21/30] drm/i915: Redirect GTT mappings to the CPU page if cache-coherent Chris Wilson
2011-04-13 15:57 ` Eric Anholt
2011-04-13 16:19 ` Chris Wilson
2011-04-13 18:35 ` [PATCH] " Chris Wilson
2011-04-13 19:13 ` Daniel Vetter
2011-04-13 19:47 ` Chris Wilson
2011-04-13 20:26 ` [PATCH] drm/i915: Prevent mmap access through the GTT of snooped pages Chris Wilson
2011-04-13 20:51 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 22/30] drm/i915: Use the LLC mode on gen6 for everything but display Chris Wilson
2011-04-13 19:15 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 23/30] drm/i915: Cache GT fifo count for SandyBridge Chris Wilson
2011-04-14 2:21 ` Ben Widawsky
2011-04-14 4:48 ` Ben Widawsky
2011-04-12 20:31 ` [PATCH 24/30] drm/i915: Refactor pwrite/pread to use single copy of get_user_pages Chris Wilson
2011-04-13 15:59 ` Eric Anholt
2011-04-13 17:24 ` Chris Wilson
2011-04-13 19:35 ` Eric Anholt
2011-04-13 19:26 ` Daniel Vetter
2011-04-13 19:56 ` Chris Wilson
2011-04-13 20:56 ` Daniel Vetter
2011-04-14 23:23 ` Ben Widawsky
2011-04-15 9:48 ` Paul Menzel
2011-04-16 8:03 ` Chris Wilson
2011-04-12 20:31 ` [PATCH 25/30] drm/i915: s/addr & ~PAGE_MASK/offset_in_page(addr)/ Chris Wilson
2011-04-12 20:31 ` [PATCH 26/30] drm/i915: Maintain fenced gpu access until we flush the fence Chris Wilson
2011-04-13 19:37 ` Daniel Vetter
2011-04-13 20:15 ` Chris Wilson
2011-04-13 20:58 ` Daniel Vetter
2011-04-13 21:37 ` Chris Wilson
2011-04-12 20:31 ` [PATCH 27/30] drm/i915: Invalidate fenced read domains upon flush Chris Wilson
2011-04-13 19:43 ` Daniel Vetter
2011-04-13 20:38 ` Chris Wilson
2011-04-13 21:02 ` Daniel Vetter
2011-04-12 20:31 ` Chris Wilson [this message]
2011-04-13 19:48 ` [PATCH 28/30] drm/i915: Pass the fence register number to be written Daniel Vetter
2011-04-12 20:31 ` [PATCH 29/30] drm/i915: Track fence setup separately from fenced object lifetime Chris Wilson
2011-04-13 20:42 ` Daniel Vetter
2011-04-13 21:56 ` Chris Wilson
2011-04-12 20:31 ` [PATCH 30/30] drm/i915: Only print out the actual number of fences for i915_error_state Chris Wilson
2011-04-13 7:26 ` i915 next Chris Wilson
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