From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 26/30] drm/i915: Maintain fenced gpu access until we flush the fence Date: Wed, 13 Apr 2011 21:37:03 +0200 Message-ID: <20110413193702.GH3660@viiv.ffwll.ch> References: <1302640318-23165-1-git-send-email-chris@chris-wilson.co.uk> <1302640318-23165-27-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ww0-f43.google.com (mail-ww0-f43.google.com [74.125.82.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 0C9BF9E93D for ; Wed, 13 Apr 2011 12:37:08 -0700 (PDT) Received: by wwb17 with SMTP id 17so946238wwb.12 for ; Wed, 13 Apr 2011 12:37:08 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1302640318-23165-27-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Apr 12, 2011 at 09:31:54PM +0100, Chris Wilson wrote: > We only want to mark the transition from unfenced GPU access by an > execbuffer, so that we are forced to flush any pending writes through > the fence before updating the register. The idea behind this change sounds good. But it completely kills the optimization to not unnecessarily stall for fences when the fence isn't in use anymore because we reset fenced_gpu_access = false only when moving to the inactive list. And when flushing the fence, which is equally late. What about moving fenced_gpu_access = false from flush_fence to process_flushing_list (and replace the one in flush_fence with an WARN_ON(fenced_gpu_access) after the flush_ring)? -Daniel -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48