[Intel-gfx] [PATCH 2/2] drm/i915/gt: Compute PP_DIR_BASE explicitly

[Chris Wilson <chris@chris-wilson.co.uk>]

Since it was not obvious that 10 == (16 - 6), do it in a couple of steps
to match up clearly with bspec.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ring_submission.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index ab58694c3320..72ca85a86af2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -635,6 +635,12 @@ static struct i915_address_space *vm_alias(struct i915_address_space *vm)
 	return vm;
 }
 
+static u32 pp_dir_base(const struct i915_ppgtt *ppgtt)
+{
+	/* 31:16 contains the cacheline (64-byte) offset into the GGTT */
+	return px_base(ppgtt->pd)->ggtt_offset / 64 << 16;
+}
+
 static void set_pp_dir(struct intel_engine_cs *engine)
 {
 	struct i915_address_space *vm = vm_alias(engine->gt->vm);
@@ -646,8 +652,7 @@ static void set_pp_dir(struct intel_engine_cs *engine)
 				 0, GEN6_MBCTL_ENABLE_BOOT_FETCH);
 
 		ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
-		ENGINE_WRITE(engine, RING_PP_DIR_BASE,
-			     px_base(ppgtt->pd)->ggtt_offset << 10);
+		ENGINE_WRITE(engine, RING_PP_DIR_BASE, pp_dir_base(ppgtt));
 	}
 }
 
@@ -1346,7 +1351,7 @@ static int load_pd_dir(struct i915_request *rq,
 
 	*cs++ = MI_LOAD_REGISTER_IMM(1);
 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
-	*cs++ = px_base(ppgtt->pd)->ggtt_offset << 10;
+	*cs++ = pp_dir_base(ppgtt);
 
 	/* Stall until the page table load is complete? */
 	*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
-- 
2.25.0

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