From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 11/15] drm/i915: Export a preallocate variant of i915_active_acquire()
Date: Mon, 16 Mar 2020 11:42:33 +0000 [thread overview]
Message-ID: <20200316114237.5436-11-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20200316114237.5436-1-chris@chris-wilson.co.uk>
Sometimes we have to be very careful not to allocate underneath a mutex
(or spinlock) and yet still want to track activity. Enter
i915_active_acquire_for_context(). This raises the activity counter on
i915_active prior to use and ensures that the fence-tree contains a slot
for the context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_active.c | 107 ++++++++++++++++++++++++++---
drivers/gpu/drm/i915/i915_active.h | 5 ++
2 files changed, 103 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c
index c4048628188a..6bb09f3020e2 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -217,11 +217,10 @@ excl_retire(struct dma_fence *fence, struct dma_fence_cb *cb)
}
static struct i915_active_fence *
-active_instance(struct i915_active *ref, struct intel_timeline *tl)
+active_instance(struct i915_active *ref, u64 idx)
{
struct active_node *node, *prealloc;
struct rb_node **p, *parent;
- u64 idx = tl->fence_context;
/*
* We track the most recently used timeline to skip a rbtree search
@@ -367,7 +366,7 @@ int i915_active_ref(struct i915_active *ref,
if (err)
return err;
- active = active_instance(ref, tl);
+ active = active_instance(ref, tl->fence_context);
if (!active) {
err = -ENOMEM;
goto out;
@@ -384,32 +383,104 @@ int i915_active_ref(struct i915_active *ref,
atomic_dec(&ref->count);
}
if (!__i915_active_fence_set(active, fence))
- atomic_inc(&ref->count);
+ __i915_active_acquire(ref);
out:
i915_active_release(ref);
return err;
}
-struct dma_fence *
-i915_active_set_exclusive(struct i915_active *ref, struct dma_fence *f)
+static struct dma_fence *
+__i915_active_set_fence(struct i915_active *ref,
+ struct i915_active_fence *active,
+ struct dma_fence *fence)
{
struct dma_fence *prev;
/* We expect the caller to manage the exclusive timeline ordering */
GEM_BUG_ON(i915_active_is_idle(ref));
+ if (is_barrier(active)) { /* proto-node used by our idle barrier */
+ /*
+ * This request is on the kernel_context timeline, and so
+ * we can use it to substitute for the pending idle-barrer
+ * request that we want to emit on the kernel_context.
+ */
+ __active_del_barrier(ref, node_from_active(active));
+ RCU_INIT_POINTER(active->fence, NULL);
+ atomic_dec(&ref->count);
+ }
+
rcu_read_lock();
- prev = __i915_active_fence_set(&ref->excl, f);
+ prev = __i915_active_fence_set(active, fence);
if (prev)
prev = dma_fence_get_rcu(prev);
else
- atomic_inc(&ref->count);
+ __i915_active_acquire(ref);
rcu_read_unlock();
return prev;
}
+static struct i915_active_fence *
+__active_lookup(struct i915_active *ref, u64 idx)
+{
+ struct active_node *node;
+ struct rb_node *p;
+
+ /* Like active_instance() but with no malloc */
+
+ node = READ_ONCE(ref->cache);
+ if (node && node->timeline == idx)
+ return &node->base;
+
+ spin_lock_irq(&ref->tree_lock);
+ GEM_BUG_ON(i915_active_is_idle(ref));
+
+ p = ref->tree.rb_node;
+ while (p) {
+ node = rb_entry(p, struct active_node, node);
+ if (node->timeline == idx) {
+ ref->cache = node;
+ spin_unlock_irq(&ref->tree_lock);
+ return &node->base;
+ }
+
+ if (node->timeline < idx)
+ p = p->rb_right;
+ else
+ p = p->rb_left;
+ }
+
+ spin_unlock_irq(&ref->tree_lock);
+
+ return NULL;
+}
+
+struct dma_fence *
+__i915_active_ref(struct i915_active *ref, u64 idx, struct dma_fence *fence)
+{
+ struct dma_fence *prev = ERR_PTR(-ENOENT);
+ struct i915_active_fence *active;
+
+ if (!i915_active_acquire_if_busy(ref))
+ return ERR_PTR(-EINVAL);
+
+ active = __active_lookup(ref, idx);
+ if (active)
+ prev = __i915_active_set_fence(ref, active, fence);
+
+ i915_active_release(ref);
+ return prev;
+}
+
+struct dma_fence *
+i915_active_set_exclusive(struct i915_active *ref, struct dma_fence *f)
+{
+ /* We expect the caller to manage the exclusive timeline ordering */
+ return __i915_active_set_fence(ref, &ref->excl, f);
+}
+
bool i915_active_acquire_if_busy(struct i915_active *ref)
{
debug_active_assert(ref);
@@ -443,6 +514,24 @@ int i915_active_acquire(struct i915_active *ref)
return err;
}
+int i915_active_acquire_for_context(struct i915_active *ref, u64 idx)
+{
+ struct i915_active_fence *active;
+ int err;
+
+ err = i915_active_acquire(ref);
+ if (err)
+ return err;
+
+ active = active_instance(ref, idx);
+ if (!active) {
+ i915_active_release(ref);
+ return -ENOMEM;
+ }
+
+ return 0; /* return with active ref */
+}
+
void i915_active_release(struct i915_active *ref)
{
debug_active_assert(ref);
@@ -748,7 +837,7 @@ int i915_active_acquire_preallocate_barrier(struct i915_active *ref,
*/
RCU_INIT_POINTER(node->base.fence, ERR_PTR(-EAGAIN));
node->base.cb.node.prev = (void *)engine;
- atomic_inc(&ref->count);
+ __i915_active_acquire(ref);
}
GEM_BUG_ON(rcu_access_pointer(node->base.fence) != ERR_PTR(-EAGAIN));
diff --git a/drivers/gpu/drm/i915/i915_active.h b/drivers/gpu/drm/i915/i915_active.h
index b3282ae7913c..65a9c560483b 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -163,6 +163,9 @@ void __i915_active_init(struct i915_active *ref,
__i915_active_init(ref, active, retire, &__mkey, &__wkey); \
} while (0)
+struct dma_fence *
+__i915_active_ref(struct i915_active *ref, u64 idx, struct dma_fence *fence);
+
int i915_active_ref(struct i915_active *ref,
struct intel_timeline *tl,
struct dma_fence *fence);
@@ -192,7 +195,9 @@ int i915_request_await_active(struct i915_request *rq,
#define I915_ACTIVE_AWAIT_ALL BIT(0)
int i915_active_acquire(struct i915_active *ref);
+int i915_active_acquire_for_context(struct i915_active *ref, u64 idx);
bool i915_active_acquire_if_busy(struct i915_active *ref);
+
void i915_active_release(struct i915_active *ref);
static inline void __i915_active_acquire(struct i915_active *ref)
--
2.20.1
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next prev parent reply other threads:[~2020-03-16 11:43 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-16 11:42 [Intel-gfx] [PATCH 01/15] drm/i915: Move GGTT fence registers under gt/ Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 02/15] drm/i915/gt: Pull restoration of GGTT fences underneath the GT Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 03/15] drm/i915: Remove manual save/resume of fence register state Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 04/15] drm/i915/gt: Allocate i915_fence_reg array Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 05/15] drm/i915/gt: Only wait for GPU activity before unbinding a GGTT fence Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 06/15] drm/i915/gt: Store the fence details on the fence Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 07/15] drm/i915/gt: Make fence revocation unequivocal Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 08/15] drm/i915/gem: Drop cached obj->bind_count Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 09/15] drm/i915: Immediately execute the fenced work Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 10/15] drm/i915/gem: Assign context id for async work Chris Wilson
2020-03-16 11:42 ` Chris Wilson [this message]
2020-03-16 11:42 ` [Intel-gfx] [PATCH 12/15] drm/i915/gem: Split eb_vma into its own allocation Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 13/15] drm/i915/gem: Separate the ww_mutex walker into its own list Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 14/15] drm/i915/gem: Asynchronous GTT unbinding Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 15/15] drm/i915/gem: Bind the fence async for execbuf Chris Wilson
2020-03-16 20:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/15] drm/i915: Move GGTT fence registers under gt/ Patchwork
2020-03-16 20:54 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-03-16 21:02 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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