From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 140F1C433E0 for ; Thu, 21 May 2020 00:38:39 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E7A212075F for ; Thu, 21 May 2020 00:38:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E7A212075F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AD8EC6E8E0; Thu, 21 May 2020 00:38:35 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7AD006E8DB for ; Thu, 21 May 2020 00:38:15 +0000 (UTC) IronPort-SDR: V03q8nwyEn5XI8elgijXHEAFC0buseeyhwB48yFKDrUBc6AarjnCZdxoPnyN3uo1E30ZCKBPjz 3lQIYjvoplzQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2020 17:38:15 -0700 IronPort-SDR: 3uiw+JYpBLTdfvCC4Vxhm6IDN3Rtz7z2PK8yA5K7s/lnjU9/JcOyfekgKbNFgpS78zprM8k7WU y+1m0Y5IWfxA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,415,1583222400"; d="scan'208";a="466720962" Received: from ldmartin1-desk.jf.intel.com ([10.165.21.151]) by fmsmga006.fm.intel.com with ESMTP; 20 May 2020 17:38:15 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Wed, 20 May 2020 17:38:00 -0700 Message-Id: <20200521003803.18936-35-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200521003803.18936-1-lucas.demarchi@intel.com> References: <20200521003803.18936-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 34/37] drm/i915/dg1: enable PORT C/D aka D/E X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fernando.pacheco@intel.com, Matthew Auld Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For DG1 we have a little of mix up wrt to DDI/port names and indexes. Bspec refers to the ports as DDIA, DDIB, DDI USBC1 and DDI USBC2 (besides the DDIA, DDIB, DDIC, DDID), but the previous naming is the most unambiguous one. This means that for any register on Display Engine we should use the index of A, B, D and E. However in some places this is not true: - VBT: uses C and D and have to be mapped to D/E - IO/Combo: uses C and D, but we already differentiate those when we created the phy vs port distinction. Ths additional mapping for VBT and phy are already covered in previous patches, so now we can initialize the DDI as D/E. Cc: Clinton Taylor Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 016f02d912e0..7f4e51ff0d63 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7213,10 +7213,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) { if (phy == PHY_NONE) return false; - else if (IS_DG1(dev_priv)) - /* FIXME: Enable only two ports for now */ - return phy <= PHY_B; - else if (IS_ROCKETLAKE(dev_priv)) + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) return phy <= PHY_D; else if (IS_ELKHARTLAKE(dev_priv)) return phy <= PHY_C; @@ -7240,7 +7237,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) { - if (IS_ROCKETLAKE(i915) && port >= PORT_D) + if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_D) return (enum phy)port - 1; else if (IS_ELKHARTLAKE(i915) && port == PORT_D) return PHY_A; @@ -16763,9 +16760,18 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) return; if (IS_DG1(dev_priv)) { - /* FIXME: Enable only two ports for now */ intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); + + /* + * Bspec lists the ports as A, B, C (USBC1) and D (USBC2). + * However from the Display Engine perspective all registers are + * actually wired to handle C and D as offsets of D/E. Instead + * of fighting all our macros for handling them specially for + * DG1, just call them D/E + */ + intel_ddi_init(dev_priv, PORT_D); + intel_ddi_init(dev_priv, PORT_E); } else if (IS_ROCKETLAKE(dev_priv)) { /* * If HTI (aka HDPORT) is enabled at boot, it may have taken -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx