Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rename is_16gb_dimm to wm_lv_0_adjust_needed

[Lucas De Marchi <lucas.demarchi@intel.com>]

On Wed, Jan 20, 2021 at 07:16:11AM -0800, Jose Souza wrote:
>As it now it is always required for GEN12+ the is_16gb_dimm name
>do not make sense for GEN12+.
>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>---
> drivers/gpu/drm/i915/i915_drv.h   |  2 +-
> drivers/gpu/drm/i915/intel_dram.c | 10 +++++-----
> drivers/gpu/drm/i915/intel_pm.c   |  2 +-
> 3 files changed, 7 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index a2ae21082b34..adc008c65b14 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -1134,7 +1134,7 @@ struct drm_i915_private {
> 	} wm;
>
> 	struct dram_info {
>-		bool is_16gb_dimm;
>+		bool wm_lv_0_adjust_needed;
> 		u8 num_channels;
> 		bool symmetric_memory;
> 		enum intel_dram_type {
>diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
>index 4871d48589f9..a5850f0f25aa 100644
>--- a/drivers/gpu/drm/i915/intel_dram.c
>+++ b/drivers/gpu/drm/i915/intel_dram.c
>@@ -207,7 +207,7 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
> 		return -EINVAL;
> 	}
>
>-	dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
>+	dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
>
> 	dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
>
>@@ -475,7 +475,7 @@ static int gen11_get_dram_info(struct drm_i915_private *i915)
> 			return ret;
> 	} else {
> 		/* Always needed for GEN12+ */
>-		i915->dram_info.is_16gb_dimm = true;
>+		i915->dram_info.wm_lv_0_adjust_needed = true;
> 	}
>
> 	return icl_pcode_read_mem_global_info(i915);
>@@ -491,7 +491,7 @@ int intel_dram_detect(struct drm_i915_private *i915)
> 	 * This is only used for the level 0 watermark latency
> 	 * w/a which does not apply to bxt/glk.
> 	 */
>-	dram_info->is_16gb_dimm = !IS_GEN9_LP(i915);
>+	dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);

comment above also needs to be updated. With that:


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>


Lucas De Marchi

>
> 	if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
> 		return 0;
>@@ -510,8 +510,8 @@ int intel_dram_detect(struct drm_i915_private *i915)
>
> 	drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);
>
>-	drm_dbg_kms(&i915->drm, "DRAM 16Gb DIMMs: %s\n",
>-		    yesno(dram_info->is_16gb_dimm));
>+	drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n",
>+		    yesno(dram_info->wm_lv_0_adjust_needed));
>
> 	return 0;
> }
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index 992fce8b8d13..f778aae19f82 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -2930,7 +2930,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
> 		 * any underrun. If not able to get Dimm info assume 16GB dimm
> 		 * to avoid any underrun.
> 		 */
>-		if (dev_priv->dram_info.is_16gb_dimm)
>+		if (dev_priv->dram_info.wm_lv_0_adjust_needed)
> 			wm[0] += 1;
>
> 	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>-- 
>2.30.0
>
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