From: Matt Atwood <matthew.s.atwood@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>;, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 22/30] drm/i915/dg2: Define MOCS table for DG2
Date: Thu, 29 Jul 2021 08:14:20 -0700 [thread overview]
Message-ID: <20210729151420.GC3816@msatwood-mobl> (raw)
In-Reply-To: <20210723174239.1551352-23-matthew.d.roper@intel.com>
On Fri, Jul 23, 2021 at 10:42:31AM -0700, Matt Roper wrote:
> Bspec: 45101, 45427
> Cc: Ramalingam C <ramalingam.c@intel.com>(v5)
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 35 +++++++++++++++++++++++++++-
> 1 file changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 0c9d0b936c20..d22ca8212092 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -341,6 +341,30 @@ static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = {
> MOCS_ENTRY(63, 0, L3_1_UC),
> };
>
> +static const struct drm_i915_mocs_entry dg2_mocs_table[] = {
> + /* UC - Coherent; GO:L3 */
> + MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)),
> + /* UC - Coherent; GO:Memory */
> + MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
> + /* UC - Non-Coherent; GO:Memory */
> + MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
> +
> + /* WB - LC */
> + MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
> +};
> +
> +static const struct drm_i915_mocs_entry dg2_mocs_table_g10_ax[] = {
> + /* Wa_14011441408: Set Go to Memory for MOCS#0 */
> + MOCS_ENTRY(0, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
> + /* UC - Coherent; GO:Memory */
> + MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
> + /* UC - Non-Coherent; GO:Memory */
> + MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
> +
> + /* WB - LC */
> + MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
> +};
> +
> enum {
> HAS_GLOBAL_MOCS = BIT(0),
> HAS_ENGINE_MOCS = BIT(1),
> @@ -367,7 +391,16 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> {
> unsigned int flags;
>
> - if (IS_XEHPSDV(i915)) {
> + if (IS_DG2(i915)) {
> + if (IS_DG2_GT_STEP(i915, G10, STEP_A0, (STEP_B0 - 1))) {
> + table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax);
> + table->table = dg2_mocs_table_g10_ax;
> + } else {
> + table->size = ARRAY_SIZE(dg2_mocs_table);
> + table->table = dg2_mocs_table;
> + }
> + table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> + } else if (IS_XEHPSDV(i915)) {
> table->size = ARRAY_SIZE(xehpsdv_mocs_table);
> table->table = xehpsdv_mocs_table;
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> --
> 2.25.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2021-07-29 15:14 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-23 17:42 [Intel-gfx] [PATCH v3 00/30] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 01/30] drm/i915/xehpsdv: Correct parameters for IS_XEHPSDV_GT_STEP() Matt Roper
2021-07-27 18:34 ` Yokoyama, Caz
2021-07-27 18:38 ` Matt Roper
2021-07-27 19:00 ` Yokoyama, Caz
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 02/30] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Matt Roper
2021-07-23 17:54 ` Lucas De Marchi
2021-07-23 17:55 ` Matt Roper
2021-07-23 19:10 ` [Intel-gfx] [PATCH v4 2/2] " Matt Roper
2021-07-24 0:47 ` Lucas De Marchi
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 03/30] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 04/30] drm/i915/xehp: Extra media engines - Part 3 (reset) Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 05/30] drm/i915/xehp: Xe_HP forcewake support Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 06/30] drm/i915/xehp: handle new steering options Matt Roper
2021-07-27 19:11 ` Yokoyama, Caz
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 07/30] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 08/30] drm/i915/xehp: Changes to ss/eu definitions Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 09/30] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 10/30] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 11/30] drm/i915/xehpsdv: Define steering tables Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 12/30] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 13/30] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 14/30] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 15/30] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 16/30] drm/i915/dg2: Add forcewake table Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 17/30] drm/i915/dg2: Update LNCF steering ranges Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 18/30] drm/i915/dg2: Add SQIDI steering Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 19/30] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 20/30] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 21/30] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-07-29 15:08 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 22/30] drm/i915/dg2: Define MOCS table for DG2 Matt Roper
2021-07-29 15:14 ` Matt Atwood [this message]
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 23/30] drm/i915/dg2: Add MPLLB programming for SNPS PHY Matt Roper
2021-07-29 15:06 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 24/30] drm/i915/dg2: Add MPLLB programming for HDMI Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 25/30] drm/i915/dg2: Add vswing programming for SNPS phys Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 26/30] drm/i915/dg2: Update modeset sequences Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 27/30] drm/i915/dg2: Wait for SNPS PHY calibration during display init Matt Roper
2021-07-24 4:19 ` kernel test robot
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 28/30] drm/i915/dg2: Update lane disable power state during PSR Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 29/30] drm/i915/dg2: Update to bigjoiner path Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 30/30] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-07-23 21:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev6) Patchwork
2021-07-23 21:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-23 21:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
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