From: Ben Widawsky <ben@bwidawsk.net>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: PIPE_CONTROL TLB invalidation fix
Date: Sun, 05 Aug 2012 18:33:25 -0700 [thread overview]
Message-ID: <6ab9644b13a64ccc497fa923f4c7d663@bwidawsk.net> (raw)
In-Reply-To: <CAKMK7uF5=HufxjqT0mbsNXD40M85eXBr-dc605e5yfggVnwfzQ@mail.gmail.com>
On 2012-08-05 11:32, Daniel Vetter wrote:
> On Fri, Jul 27, 2012 at 7:57 PM, Ben Widawsky <ben@bwidawsk.net>
> wrote:
>> On Fri, 27 Jul 2012 07:17:36 +0200
>> Daniel Vetter <daniel@ffwll.ch> wrote:
>>
>>> On Thu, Jul 26, 2012 at 04:48:43PM -0700, Ben Widawsky wrote:
>>> > The IVB simulator really doesn't like a TLB invalidate with no
>>> > post-sync operation, in fact it blows up in an assertion failure.
>>> > The documentation states that we must issue the TLB invalidate
>>> with
>>> > a CS stall: "Also Requires stall bit ([20] of DW1) set." This
>>> patch
>>> > doesn't comply with the docs, but we're able to satisfy the
>>> > simulator with this very small change, and I think simulator has
>>> > historically trumped docs.
>>> >
>>> > Note, I don't think this belongs in stable as our TLB
>>> invalidation
>>> > should be correct since we use the global invalidation per batch.
>>> > Using TLB invalidation is itself only a requirement of HW
>>> contexts.
>>> >
>>> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>>>
>>> I have another patch from Chris that kills the non-zero post-sync
>>> op
>>> workaround for ivb ... So I guess we can't do this this easily.
>>> -Daniel
>>
>> Rethink this. The need to emit the TLB invalidation as the simulator
>> dictates essentially means we cannot remove the workaround as
>> Chris' patch does.
>
> Afaik that "tlb needs a non-zero post-sync op" just means that we
> need
> to have a non-zero post-sync op in the pipe_control cmd with the tlb
> set. Whereas the gen6 wa dictatest that we need a nonzero postsync op
> _before_ the pipe_control that sets the render flush bit. So I'm
> still
> playing the dense here and don't see the connection (besides that we
> can abuse the w/a nonzero postsync op to also make the tlb flush
> happy).
>
> So can't we just set add w/a nonzeor postsync op for gen7 to make the
> simulator happy?
> -Daniel
That is certainly a possibility. I'll double check the bspec or
simulator
before I submit anything though. I'd like to make sure this doesn't
break
some other rule. For some reason I was under the assumption that we
couldn't
just emit a post sync op without several workarounds even on gen7...
--
Ben Widawsky, Intel Open Source Technology Center
prev parent reply other threads:[~2012-08-06 1:33 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-26 23:48 [PATCH] drm/i915: PIPE_CONTROL TLB invalidation fix Ben Widawsky
2012-07-27 5:17 ` Daniel Vetter
2012-07-27 17:57 ` Ben Widawsky
2012-08-05 18:32 ` Daniel Vetter
2012-08-06 1:33 ` Ben Widawsky [this message]
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