Re: [Intel-gfx] [PATCH] drm/i915/adlp: Add workaround to disable CMTG clock gating

["Souza, Jose" <jose.souza@intel.com>]

On Tue, 2021-07-27 at 16:44 +0300, Imre Deak wrote:
> The driver doesn't depend atm on the common mode timing generator
> functionality (it would be used for some power saving feature and panel
> timing synchronization), however DMC will corrupt the CMTG registers
> across DC5 entry/exit sequences unless the CMTG clock gating is
> disabled. This in turn can lead to at least the DPLL0/1 configuration
> getting stuck at their last state, which means we can't reprogram them
> to a new config.
> 
> Add the corresponding Bspec workaround to prevent the above.
> 
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h              |  3 +++
>  2 files changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index bb0aebcc3ecd3..474d723a37454 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13198,6 +13198,24 @@ static void intel_early_display_was(struct drm_i915_private *dev_priv)
>  			     KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
>  			     KBL_ARB_FILL_SPARE_14);
>  	}
> +
> +	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> +		uint32_t val;

Fixing style errors pointed by bot.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> +
> +		/*
> +		 * Wa_16011069516:adl-p[a0]
> +		 *
> +		 * All CMTG regs are unreliable until CMTG clock gating is
> +		 * disabled, so we can only assume the default CMTG_CHICKEN
> +		 * reg value and sanity check this assumption with a double
> +		 * read, which presumably returns the correct value even with
> +		 * clock gating on.
> +		 */
> +		val = intel_de_read(dev_priv, TRANS_CMTG_CHICKEN);
> +		val = intel_de_read(dev_priv, TRANS_CMTG_CHICKEN);
> +		intel_de_write(dev_priv, TRANS_CMTG_CHICKEN, DISABLE_DPT_CLK_GATING);
> +		drm_WARN_ON(&dev_priv->drm, val &~ DISABLE_DPT_CLK_GATING);
> +	}
>  }
>  
>  static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c41f9083e2338..e02bd75dd1064 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10208,6 +10208,9 @@ enum skl_power_gate {
>  #define  PORT_SYNC_MODE_MASTER_SELECT_MASK	REG_GENMASK(2, 0)
>  #define  PORT_SYNC_MODE_MASTER_SELECT(x)	REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
>  
> +#define TRANS_CMTG_CHICKEN		_MMIO(0x6fa90)
> +#define  DISABLE_DPT_CLK_GATING		REG_BIT(1)
> +
>  /* DisplayPort Transport Control */
>  #define _DP_TP_CTL_A			0x64040
>  #define _DP_TP_CTL_B			0x64140

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