On Thu, 31 Mar 2011 08:29:31 +0100, Chris Wilson wrote: > On Wed, 30 Mar 2011 14:45:11 -0700, Eric Anholt wrote: > > On Wed, 30 Mar 2011 18:16:11 +0100, Chris Wilson wrote: > > > On Wed, 30 Mar 2011 09:59:55 -0700, Eric Anholt wrote: > > > > And what about a CPU write through the GTT? > > > > > > Even on SNB these are still UC. And we should try hard not to, as the > > > specs give dire warnings about writing to snooped PTEs through the GTT. > > > (Since we will bypass the caches with the write, aiui, and cause > > > confusion.) > > > > Oh, wow. That's really bad. Reject this series if so. > > I plucked that tidbit out of the specs for the BLT engine, which has not > been rigorously updated since gen2... Though don't we also encounter a few > subtleties with movnta (__copy_from_user_nocache_nozero from pwrite) and > data in cachelines? The only tricky correctness bit for those was how to flush the little tiny movnt cache when you're done, which is "mfence". As far as other interesting notes about movnt, it doesn't mean that the destination is not in cache after the instruction -- if it was already in cache, it will likely be in cache afterwards. I don't think that has any impact on how we do our code.