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From: Isaku Yamahata <yamahata@valinux.co.jp>
To: Eduard - Gabriel Munteanu <eduard.munteanu@linux360.ro>
Cc: seabios@seabios.org, kvm@vger.kernel.org, mst@redhat.com,
	joro@8bytes.org, qemu-devel@nongnu.org, blauwirbel@gmail.com,
	av1474@comtv.ru, paul@codesourcery.com, avi@redhat.com
Subject: Re: [SeaBIOS] [PATCH 4/4] iommu: provide ACPI tables
Date: Fri, 3 Sep 2010 11:57:36 +0900	[thread overview]
Message-ID: <20100903025736.GC25721@valinux.co.jp> (raw)
In-Reply-To: <1283007778-11012-4-git-send-email-eduard.munteanu@linux360.ro>

How about the following approach?
Although I'm not sure how much multiple iommus is wanted,
it wouldn't pose single iommu limit and global variables in 3/4
would be unnecessary.

In stead of ACPI_INIT_TABLE(build_ivrs()),
something like
	foreachpci() {
	  if (class == PCI_CLASS_SYSTEM_IOMMU) {
		ACPI_INIT_TABLE(build_ivrs(bdf))
	  }
	}

and in build_ivrs()
	iommu_get_bdf() -> unnecessary.
	iommu_get_cap_offset() -> pci_find_capability(PCI_CAP_ID_SEC)
	iommu_get_misc() -> cap + IOMMU_CAP_MISC + 2
	iommu_get_base() -> read from cap + IOMMU_CAP_BAR_LOW/HIGH

thanks,

On Sat, Aug 28, 2010 at 06:02:58PM +0300, Eduard - Gabriel Munteanu wrote:
> The OS needs an ACPI IVRS table to discover and use the IOMMU.
> 
> Signed-off-by: Eduard - Gabriel Munteanu <eduard.munteanu@linux360.ro>
> ---
>  src/acpi.c |   79 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 79 insertions(+), 0 deletions(-)
> 
> diff --git a/src/acpi.c b/src/acpi.c
> index 18830dc..c267c54 100644
> --- a/src/acpi.c
> +++ b/src/acpi.c
> @@ -6,6 +6,7 @@
>  // This file may be distributed under the terms of the GNU LGPLv3 license.
>  
>  #include "acpi.h" // struct rsdp_descriptor
> +#include "iommu.h"
>  #include "util.h" // memcpy
>  #include "pci.h" // pci_find_device
>  #include "biosvar.h" // GET_EBDA
> @@ -196,6 +197,36 @@ struct srat_memory_affinity
>      u32    reserved3[2];
>  } PACKED;
>  
> +/*
> + * IVRS (I/O Virtualization Reporting Structure) table.
> + *
> + * Describes the AMD IOMMU, as per:
> + * "AMD I/O Virtualization Technology (IOMMU) Specification", rev 1.26
> + */
> +
> +struct ivrs_ivhd
> +{
> +    u8    type;
> +    u8    flags;
> +    u16   length;
> +    u16   devid;
> +    u16   capab_off;
> +    u32   iommu_base_low;
> +    u32   iommu_base_high;
> +    u16   pci_seg_group;
> +    u16   iommu_info;
> +    u32   reserved;
> +    u8    entry[0];
> +} PACKED;
> +
> +struct ivrs_table
> +{
> +    ACPI_TABLE_HEADER_DEF    /* ACPI common table header. */
> +    u32                iv_info;
> +    u32                reserved[2];
> +    struct ivrs_ivhd   ivhd;
> +} PACKED;
> +
>  #include "acpi-dsdt.hex"
>  
>  static void
> @@ -586,6 +617,53 @@ static const struct pci_device_id acpi_find_tbl[] = {
>      PCI_DEVICE_END,
>  };
>  
> +#define IVRS_SIGNATURE 0x53525649 // IVRS
> +#define IVRS_MAX_DEVS  32
> +static void *
> +build_ivrs(void)
> +{
> +    int iommu_bdf, bdf, max, i;
> +    struct ivrs_table *ivrs;
> +    struct ivrs_ivhd *ivhd;
> +
> +    iommu_bdf = pci_find_class(PCI_CLASS_SYSTEM_IOMMU);
> +    if (iommu_bdf < 0)
> +        return NULL;
> +
> +    ivrs = malloc_high(sizeof(struct ivrs_table) + 4 * IVRS_MAX_DEVS);
> +    ivrs->iv_info = iommu_get_misc() & ~0x000F;
> +
> +    ivhd = &ivrs->ivhd;
> +    ivhd->type              = 0x10;
> +    ivhd->flags             = 0;
> +    ivhd->length            = sizeof(struct ivrs_ivhd);
> +    ivhd->devid             = iommu_get_bdf();
> +    ivhd->capab_off         = iommu_get_cap_offset();
> +    ivhd->iommu_base_low    = iommu_get_base();
> +    ivhd->iommu_base_high   = 0;
> +    ivhd->pci_seg_group     = 0;
> +    ivhd->iommu_info        = 0;
> +    ivhd->reserved          = 0;
> +
> +    i = 0;
> +    foreachpci(bdf, max) {
> +        if (bdf == ivhd->devid)
> +            continue;
> +        ivhd->entry[4 * i + 0] = 2;
> +        ivhd->entry[4 * i + 1] = bdf & 0xFF;
> +        ivhd->entry[4 * i + 2] = (bdf >> 8) & 0xFF;
> +        ivhd->entry[4 * i + 3] = ~(1 << 3);
> +        ivhd->length += 4;
> +        if (++i >= IVRS_MAX_DEVS)
> +            break;
> +    }
> +
> +    build_header((void *) ivrs, IVRS_SIGNATURE,
> +                 sizeof(struct ivrs_table) + 4 * i, 1);
> +
> +    return ivrs;
> +}
> +
>  struct rsdp_descriptor *RsdpAddr;
>  
>  #define MAX_ACPI_TABLES 20
> @@ -625,6 +703,7 @@ acpi_bios_init(void)
>      ACPI_INIT_TABLE(build_madt());
>      ACPI_INIT_TABLE(build_hpet());
>      ACPI_INIT_TABLE(build_srat());
> +    ACPI_INIT_TABLE(build_ivrs());
>  
>      u16 i, external_tables = qemu_cfg_acpi_additional_tables();
>  
> -- 
> 1.7.1
> 
> 
> _______________________________________________
> SeaBIOS mailing list
> SeaBIOS@seabios.org
> http://www.seabios.org/mailman/listinfo/seabios
> 

-- 
yamahata

  reply	other threads:[~2010-09-03  2:44 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1283007778-11012-1-git-send-email-eduard.munteanu@linux360.ro>
2010-08-28 15:02 ` [PATCH 2/4] pci: add foreachcap() helper Eduard - Gabriel Munteanu
2010-09-03  2:48   ` [SeaBIOS] " Isaku Yamahata
2010-08-28 15:02 ` [PATCH 3/4] iommu: introduce AMD IOMMU support, initialize it Eduard - Gabriel Munteanu
2010-09-03  2:58   ` [SeaBIOS] " Isaku Yamahata
2010-08-28 15:02 ` [PATCH 4/4] iommu: provide ACPI tables Eduard - Gabriel Munteanu
2010-09-03  2:57   ` Isaku Yamahata [this message]
2010-09-03  2:11 ` [PATCH 1/4] pci: expand tabs to spaces in pci_ids.h and pci_regs.h Kevin O'Connor

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