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From: Nadav Amit <nadav.amit@gmail.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org, Nadav Amit <nadav.amit@gmail.com>
Subject: [kvm-unit-tests PATCH] x86: Memory barrier before setting ICR
Date: Tue, 25 Jun 2019 05:58:36 -0700	[thread overview]
Message-ID: <20190625125836.9149-1-nadav.amit@gmail.com> (raw)

The wrmsr that is used in x2apic ICR programming does not behave as a
memory barrier. There is a hidden assumption that it is. Add an explicit
memory barrier for this reason.

Signed-off-by: Nadav Amit <nadav.amit@gmail.com>
---
 lib/x86/apic.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/x86/apic.c b/lib/x86/apic.c
index bc2706e..1514730 100644
--- a/lib/x86/apic.c
+++ b/lib/x86/apic.c
@@ -2,6 +2,7 @@
 #include "apic.h"
 #include "msr.h"
 #include "processor.h"
+#include "asm/barrier.h"
 
 void *g_apic = (void *)0xfee00000;
 void *g_ioapic = (void *)0xfec00000;
@@ -71,6 +72,7 @@ static void x2apic_write(unsigned reg, u32 val)
 
 static void x2apic_icr_write(u32 val, u32 dest)
 {
+    mb();
     asm volatile ("wrmsr" : : "a"(val), "d"(dest),
                   "c"(APIC_BASE_MSR + APIC_ICR/16));
 }
-- 
2.17.1


             reply	other threads:[~2019-06-25 20:20 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-25 12:58 Nadav Amit [this message]
2019-06-27  1:07 ` [kvm-unit-tests PATCH] x86: Memory barrier before setting ICR Krish Sadhukhan
2019-06-27 17:44   ` Nadav Amit
2019-06-27 22:10     ` Krish Sadhukhan

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