From: Peter Zijlstra <peterz@infradead.org>
To: Like Xu <like.xu@linux.intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Sean Christopherson <sean.j.christopherson@intel.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
Thomas Gleixner <tglx@linutronix.de>,
ak@linux.intel.com, wei.w.wang@intel.com
Subject: Re: [PATCH v11 05/11] perf/x86: Keep LBR stack unchanged in host context for guest LBR event
Date: Tue, 19 May 2020 12:45:20 +0200 [thread overview]
Message-ID: <20200519104520.GE279861@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <dd6b0ab0-0209-e1e5-550c-24e2ad101b15@linux.intel.com>
On Tue, May 19, 2020 at 11:08:41AM +0800, Like Xu wrote:
> Sure, I could reuse cpuc->intel_ctrl_guest_mask to rewrite this part:
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index d788edb7c1f9..f1243e8211ca 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -2189,7 +2189,8 @@ static void intel_pmu_disable_event(struct perf_event
> *event)
> } else if (idx == INTEL_PMC_IDX_FIXED_BTS) {
> intel_pmu_disable_bts();
> intel_pmu_drain_bts_buffer();
> - }
> + } else if (idx == INTEL_PMC_IDX_FIXED_VLBR)
> + intel_clear_masks(event, idx);
>
> /*
> * Needs to be called after x86_pmu_disable_event,
> @@ -2271,7 +2272,8 @@ static void intel_pmu_enable_event(struct perf_event
> *event)
> if (!__this_cpu_read(cpu_hw_events.enabled))
> return;
> intel_pmu_enable_bts(hwc->config);
> - }
> + } else if (idx == INTEL_PMC_IDX_FIXED_VLBR)
> + intel_set_masks(event, idx);
> }
This makes me wonder if we can pull intel_{set,clear}_masks() out of
that if()-forest, but that's something for later...
> static void intel_pmu_add_event(struct perf_event *event)
> diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
> index b8dabf1698d6..1b30c76815dd 100644
> --- a/arch/x86/events/intel/lbr.c
> +++ b/arch/x86/events/intel/lbr.c
> @@ -552,11 +552,19 @@ void intel_pmu_lbr_del(struct perf_event *event)
> perf_sched_cb_dec(event->ctx->pmu);
> }
>
> +static inline bool vlbr_is_enabled(void)
> +{
> + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> +
> + return test_bit(INTEL_PMC_IDX_FIXED_VLBR,
> + (unsigned long *)&cpuc->intel_ctrl_guest_mask);
> +}
Maybe call this: vlbr_exclude_host() ?
> +
> void intel_pmu_lbr_enable_all(bool pmi)
> {
> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>
> - if (cpuc->lbr_users)
> + if (cpuc->lbr_users && !vlbr_is_enabled())
> __intel_pmu_lbr_enable(pmi);
> }
>
> @@ -564,7 +572,7 @@ void intel_pmu_lbr_disable_all(void)
> {
> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>
> - if (cpuc->lbr_users)
> + if (cpuc->lbr_users && !vlbr_is_enabled())
> __intel_pmu_lbr_disable();
> }
>
> @@ -706,7 +714,8 @@ void intel_pmu_lbr_read(void)
> * This could be smarter and actually check the event,
> * but this simple approach seems to work for now.
> */
> - if (!cpuc->lbr_users || cpuc->lbr_users == cpuc->lbr_pebs_users)
> + if (!cpuc->lbr_users || vlbr_is_enabled() ||
> + cpuc->lbr_users == cpuc->lbr_pebs_users)
> return;
>
> if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
>
> Is this acceptable to you ?
Yeah, looks about right. Let me stare at the rest.
next prev parent reply other threads:[~2020-05-19 10:45 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-14 8:30 [PATCH v11 00/11] Guest Last Branch Recording Enabling Like Xu
2020-05-14 8:30 ` [PATCH v11 01/11] perf/x86: Fix variable types for LBR registers Like Xu
2020-05-14 8:30 ` [PATCH v11 02/11] perf/x86/core: Refactor hw->idx checks and cleanup Like Xu
2020-05-14 8:30 ` [PATCH v11 03/11] perf/x86/lbr: Add interface to get basic information about LBR stack Like Xu
2020-05-14 8:30 ` [PATCH v11 04/11] perf/x86: Add constraint to create guest LBR event without hw counter Like Xu
2020-05-18 11:43 ` Peter Zijlstra
2020-05-14 8:30 ` [PATCH v11 05/11] perf/x86: Keep LBR stack unchanged in host context for guest LBR event Like Xu
2020-05-18 11:59 ` Peter Zijlstra
2020-05-18 12:02 ` Peter Zijlstra
2020-05-19 3:08 ` Like Xu
2020-05-19 10:45 ` Peter Zijlstra [this message]
2020-05-19 13:25 ` Xu, Like
2020-05-14 8:30 ` [PATCH v11 06/11] KVM: x86/pmu: Tweak kvm_pmu_get_msr to pass 'struct msr_data' in Like Xu
2020-05-14 8:30 ` [PATCH v11 07/11] KVM: x86: Expose MSR_IA32_PERF_CAPABILITIES for LBR record format Like Xu
2020-05-19 10:53 ` Peter Zijlstra
2020-05-19 12:19 ` Xu, Like
2020-05-19 15:12 ` Sean Christopherson
2020-05-14 8:30 ` [PATCH v11 08/11] KVM: x86/pmu: Emulate LBR feature via guest LBR event Like Xu
2020-05-19 11:00 ` Peter Zijlstra
2020-05-19 12:24 ` Xu, Like
2020-05-19 11:01 ` Peter Zijlstra
2020-05-19 12:28 ` Xu, Like
2020-05-19 11:03 ` Peter Zijlstra
2020-05-19 12:40 ` Xu, Like
2020-05-14 8:30 ` [PATCH v11 09/11] KVM: x86/pmu: Release guest LBR event via vPMU lazy release mechanism Like Xu
2020-05-14 8:30 ` [PATCH v11 10/11] KVM: x86/pmu: Check guest LBR availability in case host reclaims them Like Xu
2020-05-19 11:15 ` Peter Zijlstra
2020-05-19 13:10 ` Xu, Like
2020-05-19 14:57 ` Peter Zijlstra
2020-05-20 2:01 ` Xu, Like
2020-05-27 8:17 ` Like Xu
2020-05-14 8:30 ` [PATCH v11 11/11] KVM: x86/pmu: Reduce the overhead of LBR passthrough or cancellation Like Xu
2020-05-27 8:28 ` [PATCH v11 00/11] Guest Last Branch Recording Enabling Xu, Like
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