From: Like Xu <like.xu@linux.intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>, peterz@infradead.org
Cc: Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
weijiang.yang@intel.com, eranian@google.com,
wei.w.wang@intel.com, kvm@vger.kernel.org, x86@kernel.org,
linux-kernel@vger.kernel.org, Like Xu <like.xu@linux.intel.com>,
Andi Kleen <andi.kleen@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>
Subject: [PATCH v3 1/5] KVM: x86/pmu: Add pebs_vmx support for ATOM_TREMONT
Date: Wed, 12 May 2021 16:44:42 +0800 [thread overview]
Message-ID: <20210512084446.342526-2-like.xu@linux.intel.com> (raw)
In-Reply-To: <20210512084446.342526-1-like.xu@linux.intel.com>
The ATOM_TREMONT platform also supports the EPT-Friendly PEBS capability
and we can also safely enable guest PEBS. Per Intel SDM, the PDIR counter
on non-Ice Lake platforms is always GP counter 1;
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Andi Kleen <andi.kleen@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
---
arch/x86/events/intel/core.c | 1 +
arch/x86/kvm/pmu.c | 5 ++---
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index e7bbd9aab175..4404987bbc57 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5826,6 +5826,7 @@ __init int intel_pmu_init(void)
case INTEL_FAM6_ATOM_TREMONT_D:
case INTEL_FAM6_ATOM_TREMONT:
case INTEL_FAM6_ATOM_TREMONT_L:
+ x86_pmu.pebs_vmx = 1;
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index 4798bf991b60..8c700a7930c4 100644
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -151,9 +151,8 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
* the accuracy of the PEBS profiling result, because the "event IP"
* in the PEBS record is calibrated on the guest side.
*/
- attr.precise_ip = 1;
- if (x86_match_cpu(vmx_icl_pebs_cpu) && pmc->idx == 32)
- attr.precise_ip = 3;
+ attr.precise_ip = x86_match_cpu(vmx_icl_pebs_cpu) ?
+ ((pmc->idx == 32) ? 3 : 1) : ((pmc->idx == 1) ? 3 : 1);
}
event = perf_event_create_kernel_counter(&attr, -1, current,
--
2.31.1
next prev parent reply other threads:[~2021-05-12 8:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-12 8:44 [PATCH v3 0/5] KVM: x86/pmu: Add support to enable guest PEBS via PT Like Xu
2021-05-12 8:44 ` Like Xu [this message]
2021-05-12 8:44 ` [PATCH v3 2/5] KVM: x86/pmu: Add the base address parameter for get_fixed_pmc() Like Xu
2021-05-12 8:44 ` [PATCH v3 3/5] KVM: x86/pmu: Add counter reload MSR emulation for all counters Like Xu
2021-05-12 8:44 ` [PATCH v3 4/5] KVM: x86/pmu: Add counter reload registers to the MSR-load list Like Xu
2021-05-12 8:44 ` [PATCH v3 5/5] KVM: x86/pmu: Expose PEBS-via-PT in the KVM supported capabilities Like Xu
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