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([2001:b07:6468:f312:bddb:697c:bea8:abc]) by smtp.gmail.com with ESMTPSA id g3sm25430861wrw.47.2020.04.09.02.43.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Apr 2020 02:43:31 -0700 (PDT) Subject: Re: [PATCH v2] x86/kvm: Disable KVM_ASYNC_PF_SEND_ALWAYS To: Andy Lutomirski , Thomas Gleixner , Andrew Cooper Cc: Sean Christopherson , Vivek Goyal , Peter Zijlstra , LKML , X86 ML , kvm list , stable References: <20200407172140.GB64635@redhat.com> <772A564B-3268-49F4-9AEA-CDA648F6131F@amacapital.net> <87eeszjbe6.fsf@nanos.tec.linutronix.de> <874ktukhku.fsf@nanos.tec.linutronix.de> <274f3d14-08ac-e5cc-0b23-e6e0274796c8@redhat.com> <20200408153413.GA11322@linux.intel.com> <87d08hc0vz.fsf@nanos.tec.linutronix.de> From: Paolo Bonzini Message-ID: <47a7593e-e035-1b48-c6d7-cd6f78a2f6e2@redhat.com> Date: Thu, 9 Apr 2020 11:43:29 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 09/04/20 06:50, Andy Lutomirski wrote: > The big problem is that #VE doesn't exist on AMD, and I really think > that any fancy protocol we design should work on AMD. I have no > problem with #VE being a nifty optimization to the protocol on Intel, > but it should *work* without #VE. Yes and unfortunately AMD does not like to inject a non-existing exception. Intel only requires the vector to be <=31, but AMD wants the vector to correspond to an exception. However, software injection is always possible and AMD even suggests that you use software injection for ICEBP and, on older processors, the INT instruction. Paolo