Re: [PATCH kvm-unit-tests] arm/arm64: PL031: Fix check_rtc_irq

["Graf (AWS), Alexander" <graf@amazon.de>]

> Am 28.11.2019 um 17:56 schrieb "drjones@redhat.com" <drjones@redhat.com>:
> 
> Since QEMU commit 83ad95957c7e ("pl031: Expose RTCICR as proper WC
> register") the PL031 test gets into an infinite loop. Now we must
> write bit zero of RTCICR to clear the IRQ status. Before, writing
> anything to RTCICR would work. As '1' is a member of 'anything'
> writing it should work for old QEMU as well.
> 
> Cc: Alexander Graf <graf@amazon.com>
> Signed-off-by: Andrew Jones <drjones@redhat.com>

Reviewed-by: Alexander Graf <graf@amazon.com>

Sorry for introducing a test case on code that I then modify, without updating the test case as well :)

Alex


> ---
> arm/pl031.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arm/pl031.c b/arm/pl031.c
> index 1f63ef13994f..3b75fd653e96 100644
> --- a/arm/pl031.c
> +++ b/arm/pl031.c
> @@ -143,8 +143,8 @@ static void irq_handler(struct pt_regs *regs)
>        report(readl(&pl031->ris) == 1, "  RTC RIS == 1");
>        report(readl(&pl031->mis) == 1, "  RTC MIS == 1");
> 
> -        /* Writing any value should clear IRQ status */
> -        writel(0x80000000ULL, &pl031->icr);
> +        /* Writing one to bit zero should clear IRQ status */
> +        writel(1, &pl031->icr);
> 
>        report(readl(&pl031->ris) == 0, "  RTC RIS == 0");
>        report(readl(&pl031->mis) == 0, "  RTC MIS == 0");
> -- 
> 2.21.0
> 



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