From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02C0DC433ED for ; Wed, 14 Apr 2021 22:32:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CA20261019 for ; Wed, 14 Apr 2021 22:32:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231978AbhDNWdA (ORCPT ); Wed, 14 Apr 2021 18:33:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229903AbhDNWdA (ORCPT ); Wed, 14 Apr 2021 18:33:00 -0400 Received: from mail-io1-xd2f.google.com (mail-io1-xd2f.google.com [IPv6:2607:f8b0:4864:20::d2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAC82C061574 for ; Wed, 14 Apr 2021 15:32:36 -0700 (PDT) Received: by mail-io1-xd2f.google.com with SMTP id a9so11401066ioc.8 for ; Wed, 14 Apr 2021 15:32:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=DnWpmyuBcVLMh+o254nNZjs/ViGAgPIT2BWu82a9qds=; b=VBQkmczcFZIy8vNoASuNLjaR7Mqq4uAMvQbmVI31prjpKqnoQ8DYYWS/Vr64FewoaJ t+5Z8Vez2c/GrpehDiF/LLnGO3ELLsNVQDb8JmfBoO5DZ38ECyWeAFHhkde39wCh1dAV 8KFjbXmGMdDMMWu8b6fIseMYcUJyTpPnzuXdfZI8bBiEJUp5EnsCaSzRonsSp34GSTFt cGOjTskLLPCkEeZ91Vqyq0es38h+7I2VVq6+ZICZXMXFtp2+ZfJt55x1yl6tlqS2BiRw COmM3IEw/1lV4CpM9RR+oeBMxF+so8nr2YMSAg5tmBdAwYVKUDDvIY7eXfHoYLeOYAFt M2+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=DnWpmyuBcVLMh+o254nNZjs/ViGAgPIT2BWu82a9qds=; b=OVz+wsIbajbjT8Smh3A7fH3z33z2F26reCyI3qgmJScOaUuTUQp8Q6+A4JjCXSIqUS CiNc0BnRb+FGtmawg1PKjx/Y2+CsL3P2q4nXDbraxs69MRF6+q3jnSI/4YouZ8MZZdbw Ow8/FFkaT/OuE1dNxdDOHtba7fp59AhDk6UvnQH6Ke4g1uDavISgiPW9XjnPg1PtST2R 630m4qVQAJaW4Dsz4l3KYx5txO6jqwXoI5R7yG7F6CBdaUCHJb5zykds44M+XAl/qdrX 3eOAU8nZUmBQDUudVIIDvitBxlURjH1TJt5BCrUoE/1n6VTFqJ5z9SicDagtnQdk7zCm KViw== X-Gm-Message-State: AOAM531+f6rg4Kfw0KCiHdckCgwuuvPkBxIAsZewpLQrqi4OY/Bs/V9l UvMXchipUVnWy00NZOJ1vKGjF9jZxavA3D5H0H0= X-Google-Smtp-Source: ABdhPJzlHwyWvinrhm2Yv5H+jUvhG4+4quL/QYdBBVc8w8nMH9ycirhBlndVFnE//9LtCOb91HnQ1eLdgxpG+hRYNFc= X-Received: by 2002:a05:6638:1211:: with SMTP id n17mr198838jas.26.1618439556144; Wed, 14 Apr 2021 15:32:36 -0700 (PDT) MIME-Version: 1.0 References: <20210412065246.1853-1-jiangyifei@huawei.com> <20210412065246.1853-4-jiangyifei@huawei.com> In-Reply-To: <20210412065246.1853-4-jiangyifei@huawei.com> From: Alistair Francis Date: Thu, 15 Apr 2021 08:32:09 +1000 Message-ID: Subject: Re: [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu To: Yifei Jiang Cc: "qemu-devel@nongnu.org Developers" , "open list:RISC-V" , Bin Meng , Sagar Karandikar , "open list:Overall" , libvir-list@redhat.com, Bastian Koppelmann , Anup Patel , yinyipeng , Alistair Francis , kvm-riscv@lists.infradead.org, Palmer Dabbelt , fanliang@huawei.com, "Wubin (H)" , Zhanghailiang Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Mon, Apr 12, 2021 at 4:53 PM Yifei Jiang wrote: > > Get isa info from kvm while kvm init. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin > --- > target/riscv/kvm.c | 27 ++++++++++++++++++++++++++- > 1 file changed, 26 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 687dd4b621..0d924be33f 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -38,6 +38,18 @@ > #include "qemu/log.h" > #include "hw/loader.h" > > +static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx) > +{ > + __u64 id = KVM_REG_RISCV | type | idx; Can you use uint64_t instead of __u64? Once that is fixed: Reviewed-by: Alistair Francis Alistair > + > + if (riscv_cpu_is_32bit(env)) { > + id |= KVM_REG_SIZE_U32; > + } else { > + id |= KVM_REG_SIZE_U64; > + } > + return id; > +} > + > const KVMCapabilityInfo kvm_arch_required_capabilities[] = { > KVM_CAP_LAST_INFO > }; > @@ -79,7 +91,20 @@ void kvm_arch_init_irq_routing(KVMState *s) > > int kvm_arch_init_vcpu(CPUState *cs) > { > - return 0; > + int ret = 0; > + target_ulong isa; > + RISCVCPU *cpu = RISCV_CPU(cs); > + CPURISCVState *env = &cpu->env; > + __u64 id; > + > + id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa)); > + ret = kvm_get_one_reg(cs, id, &isa); > + if (ret) { > + return ret; > + } > + env->misa = isa | RVXLEN; > + > + return ret; > } > > int kvm_arch_msi_data_to_gsi(uint32_t data) > -- > 2.19.1 > >