From: Borislav Petkov <bp@alien8.de>
To: Brijesh Singh <brijesh.singh@amd.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, tglx@linutronix.de, jroedel@suse.de,
thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com,
dave.hansen@intel.com, rientjes@google.com, seanjc@google.com,
peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com
Subject: Re: [PATCH Part1 RFC v2 03/20] x86/sev: Add support for hypervisor feature VMGEXIT
Date: Tue, 11 May 2021 12:01:37 +0200 [thread overview]
Message-ID: <YJpWAY+ayATSn6nN@zn.tnic> (raw)
In-Reply-To: <20210430121616.2295-4-brijesh.singh@amd.com>
On Fri, Apr 30, 2021 at 07:15:59AM -0500, Brijesh Singh wrote:
> Version 2 of GHCB specification introduced advertisement of a features
> that are supported by the hypervisor. Define the GHCB MSR protocol and NAE
> for the hypervisor feature request and query the feature during the GHCB
> protocol negotitation. See the GHCB specification for more details.
>
> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
> ---
> arch/x86/include/asm/sev-common.h | 17 +++++++++++++++++
> arch/x86/include/uapi/asm/svm.h | 2 ++
> arch/x86/kernel/sev-shared.c | 24 ++++++++++++++++++++++++
> 3 files changed, 43 insertions(+)
>
> diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h
> index 9f1b66090a4c..8142e247d8da 100644
> --- a/arch/x86/include/asm/sev-common.h
> +++ b/arch/x86/include/asm/sev-common.h
> @@ -51,6 +51,22 @@
> #define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12
> #define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK 0xfffffffffffff
>
> +/* GHCB Hypervisor Feature Request */
> +#define GHCB_MSR_HV_FEATURES_REQ 0x080
> +#define GHCB_MSR_HV_FEATURES_RESP 0x081
> +#define GHCB_MSR_HV_FEATURES_POS 12
> +#define GHCB_MSR_HV_FEATURES_MASK 0xfffffffffffffUL
> +#define GHCB_MSR_HV_FEATURES_RESP_VAL(v) \
> + (((v) >> GHCB_MSR_HV_FEATURES_POS) & GHCB_MSR_HV_FEATURES_MASK)
> +
> +#define GHCB_HV_FEATURES_SNP BIT_ULL(0)
> +#define GHCB_HV_FEATURES_SNP_AP_CREATION \
> + (BIT_ULL(1) | GHCB_HV_FEATURES_SNP)
> +#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION \
> + (BIT_ULL(2) | GHCB_HV_FEATURES_SNP_AP_CREATION)
> +#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER \
> + (BIT_ULL(3) | GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION)
Please add those in the patches which use them - not in bulk here.
And GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER is a mouthfull and
looks like BIOS code to me. But this is still the kernel, remember? :-)
So let's do
GHCB_MSR_HV_FT_*
GHCB_SNP_AP_CREATION
GHCB_SNP_RESTRICTED_INJ
GHCB_SNP_RESTRICTED_INJ_TMR
and so on so that we can all keep our sanity when reading that code.
> +
> #define GHCB_MSR_TERM_REQ 0x100
> #define GHCB_MSR_TERM_REASON_SET_POS 12
> #define GHCB_MSR_TERM_REASON_SET_MASK 0xf
> @@ -62,6 +78,7 @@
>
> #define GHCB_SEV_ES_REASON_GENERAL_REQUEST 0
> #define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED 1
> +#define GHCB_SEV_ES_REASON_SNP_UNSUPPORTED 2
I remember asking for those to get shortened too
GHCB_SEV_ES_GEN_REQ
GHCB_SEV_ES_PROT_UNSUPPORTED
GHCB_SEV_ES_SNP_UNSUPPORTED
Perhaps in a prepatch?
> #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK)
>
> diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h
> index 554f75fe013c..7fbc311e2de1 100644
> --- a/arch/x86/include/uapi/asm/svm.h
> +++ b/arch/x86/include/uapi/asm/svm.h
> @@ -108,6 +108,7 @@
> #define SVM_VMGEXIT_AP_JUMP_TABLE 0x80000005
> #define SVM_VMGEXIT_SET_AP_JUMP_TABLE 0
> #define SVM_VMGEXIT_GET_AP_JUMP_TABLE 1
> +#define SVM_VMGEXIT_HYPERVISOR_FEATURES 0x8000fffd
SVM_VMGEXIT_HV_FT
you get the idea.
> #define SVM_VMGEXIT_UNSUPPORTED_EVENT 0x8000ffff
>
> #define SVM_EXIT_ERR -1
> @@ -215,6 +216,7 @@
> { SVM_VMGEXIT_NMI_COMPLETE, "vmgexit_nmi_complete" }, \
> { SVM_VMGEXIT_AP_HLT_LOOP, "vmgexit_ap_hlt_loop" }, \
> { SVM_VMGEXIT_AP_JUMP_TABLE, "vmgexit_ap_jump_table" }, \
> + { SVM_VMGEXIT_HYPERVISOR_FEATURES, "vmgexit_hypervisor_feature" }, \
> { SVM_EXIT_ERR, "invalid_guest_state" }
>
>
> diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c
> index 48a47540b85f..874f911837db 100644
> --- a/arch/x86/kernel/sev-shared.c
> +++ b/arch/x86/kernel/sev-shared.c
> @@ -20,6 +20,7 @@
> * out when the .bss section is later cleared.
> */
> static u16 ghcb_version __section(".data") = 0;
> +static u64 hv_features __section(".data") = 0;
ERROR: do not initialise statics to 0
#181: FILE: arch/x86/kernel/sev-shared.c:23:
+static u64 hv_features __section(".data") = 0;
> static bool __init sev_es_check_cpu_features(void)
> {
> @@ -49,6 +50,26 @@ static void __noreturn sev_es_terminate(unsigned int reason)
> asm volatile("hlt\n" : : : "memory");
> }
>
> +static bool ghcb_get_hv_features(void)
Used only once here - no need for the ghcb_ prefix.
> +{
> + u64 val;
> +
> + /* The hypervisor features are available from version 2 onward. */
> + if (ghcb_version < 2)
> + return true;
return false;
no?
Also, this should be done differently:
if (ghcb_version >= 2)
get_hv_features();
at the call site.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2021-05-11 10:01 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-30 12:15 [PATCH Part1 RFC v2 00/20] Add AMD Secure Nested Paging (SEV-SNP) Guest Support Brijesh Singh
2021-04-30 12:15 ` [PATCH Part1 RFC v2 01/20] x86/sev: Define the GHCB MSR protocol for AP reset hold Brijesh Singh
2021-04-30 12:15 ` [PATCH Part1 RFC v2 02/20] x86/sev: Save the negotiated GHCB version Brijesh Singh
2021-05-11 9:23 ` Borislav Petkov
2021-05-11 18:29 ` Brijesh Singh
2021-05-11 18:41 ` Borislav Petkov
2021-05-12 14:03 ` Brijesh Singh
2021-05-12 14:31 ` Borislav Petkov
2021-05-12 15:03 ` Brijesh Singh
2021-04-30 12:15 ` [PATCH Part1 RFC v2 03/20] x86/sev: Add support for hypervisor feature VMGEXIT Brijesh Singh
2021-05-11 10:01 ` Borislav Petkov [this message]
2021-05-11 18:53 ` Brijesh Singh
2021-05-17 14:40 ` Borislav Petkov
2021-04-30 12:16 ` [PATCH Part1 RFC v2 04/20] x86/sev: Increase the GHCB protocol version Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 05/20] x86/sev: Define SNP Page State Change VMGEXIT structure Brijesh Singh
2021-05-18 10:41 ` Borislav Petkov
2021-05-18 15:06 ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 06/20] x86/sev: Define SNP guest request NAE events Brijesh Singh
2021-05-18 10:45 ` Borislav Petkov
2021-05-18 13:42 ` Brijesh Singh
2021-05-18 13:54 ` Borislav Petkov
2021-05-18 14:13 ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 07/20] x86/sev: Define error codes for reason set 1 Brijesh Singh
2021-05-18 11:05 ` Borislav Petkov
2021-04-30 12:16 ` [PATCH Part1 RFC v2 08/20] x86/mm: Add sev_snp_active() helper Brijesh Singh
2021-05-18 18:11 ` Borislav Petkov
2021-05-19 17:28 ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 09/20] x86/sev: check SEV-SNP features support Brijesh Singh
2021-05-20 16:02 ` Borislav Petkov
2021-05-20 17:40 ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 10/20] x86/sev: Add a helper for the PVALIDATE instruction Brijesh Singh
2021-04-30 13:05 ` Brijesh Singh
2021-05-20 17:32 ` Borislav Petkov
2021-05-20 17:44 ` Brijesh Singh
2021-05-20 17:51 ` Borislav Petkov
2021-05-20 17:57 ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 11/20] x86/compressed: Add helper for validating pages in the decompression stage Brijesh Singh
2021-05-20 17:52 ` Borislav Petkov
2021-05-20 18:05 ` Brijesh Singh
2021-05-25 10:18 ` Borislav Petkov
2021-04-30 12:16 ` [PATCH Part1 RFC v2 12/20] x86/compressed: Register GHCB memory when SEV-SNP is active Brijesh Singh
2021-05-25 10:41 ` Borislav Petkov
2021-04-30 12:16 ` [PATCH Part1 RFC v2 13/20] x86/sev: " Brijesh Singh
2021-05-25 11:11 ` Borislav Petkov
2021-05-25 14:28 ` Brijesh Singh
2021-05-25 14:35 ` Borislav Petkov
2021-05-25 14:47 ` Brijesh Singh
2021-05-26 9:57 ` Borislav Petkov
2021-05-26 13:23 ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 14/20] x86/sev: Add helper for validating pages in early enc attribute changes Brijesh Singh
2021-05-26 10:39 ` Borislav Petkov
2021-05-26 13:34 ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 15/20] x86/kernel: Make the bss.decrypted section shared in RMP table Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 16/20] x86/kernel: Validate rom memory before accessing when SEV-SNP is active Brijesh Singh
2021-05-27 11:49 ` Borislav Petkov
2021-05-27 12:12 ` Brijesh Singh
2021-05-27 12:23 ` Borislav Petkov
2021-05-27 12:56 ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 17/20] x86/mm: Add support to validate memory when changing C-bit Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 18/20] x86/boot: Add Confidential Computing address to setup_header Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 19/20] x86/sev: Register SNP guest request platform device Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 20/20] virt: Add SEV-SNP guest driver Brijesh Singh
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