From: Xiaoyao Li <xiaoyao.li@linux.intel.com>
To: Tao Xu <tao3.xu@intel.com>,
pbonzini@redhat.com, rkrcmar@redhat.com, corbet@lwn.net,
tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
hpa@zytor.com, sean.j.christopherson@intel.com,
fenghua.yu@intel.com
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, jingqi.liu@intel.com
Subject: Re: [PATCH RESEND v3 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
Date: Mon, 17 Jun 2019 14:31:25 +0800 [thread overview]
Message-ID: <ea1fc40b-8f80-d5f0-6c97-adb245599e07@linux.intel.com> (raw)
In-Reply-To: <d99b2ae1-38fc-0b71-2613-8131decc923a@intel.com>
On 6/17/2019 11:32 AM, Xiaoyao Li wrote:
>
>
> On 6/16/2019 5:55 PM, Tao Xu wrote:
>> UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H
>> to determines the maximum time in TSC-quanta that the processor can
>> reside
>> in either C0.1 or C0.2.
>>
>> This patch emulates MSR IA32_UMWAIT_CONTROL in guest and differentiate
>> IA32_UMWAIT_CONTROL between host and guest. The variable
>> mwait_control_cached in arch/x86/power/umwait.c caches the MSR value, so
>> this patch uses it to avoid frequently rdmsr of IA32_UMWAIT_CONTROL.
>>
>> Co-developed-by: Jingqi Liu <jingqi.liu@intel.com>
>> Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
>> Signed-off-by: Tao Xu <tao3.xu@intel.com>
>> ---
>> arch/x86/kvm/vmx/vmx.c | 36 ++++++++++++++++++++++++++++++++++++
>> arch/x86/kvm/vmx/vmx.h | 3 +++
>> arch/x86/power/umwait.c | 3 ++-
>> 3 files changed, 41 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
>> index b35bfac30a34..f33a25e82cb8 100644
>> --- a/arch/x86/kvm/vmx/vmx.c
>> +++ b/arch/x86/kvm/vmx/vmx.c
>> @@ -1679,6 +1679,12 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu,
>> struct msr_data *msr_info)
>> #endif
>> case MSR_EFER:
>> return kvm_get_msr_common(vcpu, msr_info);
>> + case MSR_IA32_UMWAIT_CONTROL:
>> + if (!vmx_waitpkg_supported())
>> + return 1;
>> +
>> + msr_info->data = vmx->msr_ia32_umwait_control;
>> + break;
>> case MSR_IA32_SPEC_CTRL:
>> if (!msr_info->host_initiated &&
>> !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
>> @@ -1841,6 +1847,15 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu,
>> struct msr_data *msr_info)
>> return 1;
>> vmcs_write64(GUEST_BNDCFGS, data);
>> break;
>> + case MSR_IA32_UMWAIT_CONTROL:
>> + if (!vmx_waitpkg_supported())
>> + return 1;
>> +
>> + if (!data)
>> + break;
>> +
>
> Why cannot clear it to zero?
>
>> + vmx->msr_ia32_umwait_control = data;
>> + break;
>> case MSR_IA32_SPEC_CTRL:
>> if (!msr_info->host_initiated &&
>> !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
>> @@ -4126,6 +4141,8 @@ static void vmx_vcpu_reset(struct kvm_vcpu
>> *vcpu, bool init_event)
>> vmx->rmode.vm86_active = 0;
>> vmx->spec_ctrl = 0;
>> + vmx->msr_ia32_umwait_control = 0;
>> +
>> vcpu->arch.microcode_version = 0x100000000ULL;
>> vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
>> kvm_set_cr8(vcpu, 0);
>> @@ -6339,6 +6356,23 @@ static void atomic_switch_perf_msrs(struct
>> vcpu_vmx *vmx)
>> msrs[i].host, false);
>> }
>> +static void atomic_switch_ia32_umwait_control(struct vcpu_vmx *vmx)
>> +{
>> + u64 host_umwait_control;
>> +
>> + if (!vmx_waitpkg_supported())
>> + return;
>> +
>> + host_umwait_control = umwait_control_cached;
>> +
>
> It's redundant to define host_umwait_control and this line, we can just
> use umwait_control_cached.
>
>> + if (vmx->msr_ia32_umwait_control != host_umwait_control)
>> + add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
>> + vmx->msr_ia32_umwait_control,
>> + host_umwait_control, false);
>
> The bit 1 is reserved, at least, we need to do below to ensure not
> modifying the reserved bit:
>
> guest_val = (vmx->msr_ia32_umwait_control & ~BIT_ULL(1)) |
> (host_val & BIT_ULL(1))
>
I find a better solution to ensure reserved bit 1 not being modified in
vmx_set_msr() as below:
if((data ^ umwait_control_cached) & BIT_ULL(1))
return 1;
>> + else
>> + clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
>> +}
>> +
>> static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
>> {
>> vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
>> @@ -6447,6 +6481,8 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
>> atomic_switch_perf_msrs(vmx);
>> + atomic_switch_ia32_umwait_control(vmx);
>> +
>> vmx_update_hv_timer(vcpu);
>> /*
>> diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
>> index 61128b48c503..8485bec7c38a 100644
>> --- a/arch/x86/kvm/vmx/vmx.h
>> +++ b/arch/x86/kvm/vmx/vmx.h
>> @@ -14,6 +14,8 @@
>> extern const u32 vmx_msr_index[];
>> extern u64 host_efer;
>> +extern u32 umwait_control_cached;
>> +
>> #define MSR_TYPE_R 1
>> #define MSR_TYPE_W 2
>> #define MSR_TYPE_RW 3
>> @@ -194,6 +196,7 @@ struct vcpu_vmx {
>> #endif
>> u64 spec_ctrl;
>> + u64 msr_ia32_umwait_control;
>> u32 vm_entry_controls_shadow;
>> u32 vm_exit_controls_shadow;
>> diff --git a/arch/x86/power/umwait.c b/arch/x86/power/umwait.c
>> index 7fa381e3fd4e..2e6ce4cbccb3 100644
>> --- a/arch/x86/power/umwait.c
>> +++ b/arch/x86/power/umwait.c
>> @@ -9,7 +9,8 @@
>> * MSR value. By default, umwait max time is 100000 in TSC-quanta
>> and C0.2
>> * is enabled
>> */
>> -static u32 umwait_control_cached = 100000;
>> +u32 umwait_control_cached = 100000;
>> +EXPORT_SYMBOL_GPL(umwait_control_cached);
>> /*
>> * Serialize access to umwait_control_cached and IA32_UMWAIT_CONTROL
>> MSR
>>
next prev parent reply other threads:[~2019-06-17 6:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-16 9:55 [PATCH RESEND v3 0/3] KVM: x86: Enable user wait instructions Tao Xu
2019-06-16 9:55 ` [PATCH RESEND v3 1/3] KVM: x86: add support for " Tao Xu
2019-06-16 9:55 ` [PATCH RESEND v3 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL Tao Xu
2019-06-17 3:32 ` Xiaoyao Li
2019-06-17 6:31 ` Xiaoyao Li [this message]
2019-06-17 15:50 ` Radim Krčmář
2019-06-17 15:54 ` Xiaoyao Li
2019-06-18 2:40 ` Tao Xu
2019-06-18 3:04 ` Tao Xu
2019-06-16 9:55 ` [PATCH RESEND v3 3/3] KVM: vmx: handle vm-exit for UMWAIT and TPAUSE Tao Xu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ea1fc40b-8f80-d5f0-6c97-adb245599e07@linux.intel.com \
--to=xiaoyao.li@linux.intel.com \
--cc=bp@alien8.de \
--cc=corbet@lwn.net \
--cc=fenghua.yu@intel.com \
--cc=hpa@zytor.com \
--cc=jingqi.liu@intel.com \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=pbonzini@redhat.com \
--cc=rkrcmar@redhat.com \
--cc=sean.j.christopherson@intel.com \
--cc=tao3.xu@intel.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).