From: "Xu, Like" <like.xu@intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
eranian@google.com, kvm@vger.kernel.org,
Ingo Molnar <mingo@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Thomas Gleixner <tglx@linutronix.de>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
Andi Kleen <andi@firstfloor.org>,
Kan Liang <kan.liang@linux.intel.com>,
wei.w.wang@intel.com, luwei.kang@intel.com,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 06/17] KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS
Date: Fri, 15 Jan 2021 23:29:22 +0800 [thread overview]
Message-ID: <ff0ccfdd-e5e5-1a6d-57ff-9117a44a30b2@intel.com> (raw)
In-Reply-To: <YAGqrIqTxNU/PMxo@hirez.programming.kicks-ass.net>
On 2021/1/15 22:46, Peter Zijlstra wrote:
> On Mon, Jan 04, 2021 at 09:15:31PM +0800, Like Xu wrote:
>
>> + if (cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask) {
>> + arr[1].msr = MSR_IA32_PEBS_ENABLE;
>> + arr[1].host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask;
>> + arr[1].guest = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask;
>> + /*
>> + * The guest PEBS will be disabled once the host PEBS is enabled
>> + * since the both enabled case may brings a unknown PMI to
>> + * confuse host and the guest PEBS overflow PMI would be missed.
>> + */
>> + if (arr[1].host)
>> + arr[1].guest = 0;
>> + arr[0].guest |= arr[1].guest;
>> + *nr = 2;
> Elsewhere you write:
>
>> When we have a PEBS PMI due to guest workload and vm-exits,
>> the code path from vm-exit to the host PEBS PMI handler may also
>> bring PEBS PMI and mark the status bit. The current PMI handler
>> can't distinguish them and would treat the later one as a suspicious
>> PMI and output a warning.
> So the reason isn't that spurious PMIs are tedious, but that the
> hardware is actually doing something weird.
>
> Or am I not reading things straight?
I think the PEBS facility works as expected because in the both enabled case,
the first PEBS PMI is generated from host counter 1 based on guest
interrupt_threshold
and the later PEBS PMI could be generated from host counter 2 based on host
interrupt_threshold.
Therefore, if we adjust the overflow value to a small value, so that the
number of
instructions from vm-exit to global ctrl disabling could be enough big to
trigger PEBS PMI.
Do you think this is weird, or do you see other possibilities ?
next prev parent reply other threads:[~2021-01-15 15:30 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-04 13:15 [PATCH v3 00/17] KVM: x86/pmu: Add support to enable Guest PEBS via DS Like Xu
2021-01-04 13:15 ` [PATCH v3 01/17] KVM: x86/pmu: Set MSR_IA32_MISC_ENABLE_EMON bit when vPMU is enabled Like Xu
2021-01-04 13:15 ` [PATCH v3 02/17] KVM: x86/pmu: Use IA32_PERF_CAPABILITIES to adjust features visibility Like Xu
2021-01-04 13:15 ` [PATCH v3 03/17] KVM: x86/pmu: Introduce the ctrl_mask value for fixed counter Like Xu
2021-01-13 18:06 ` Peter Zijlstra
2021-01-14 1:58 ` Xu, Like
2021-01-04 13:15 ` [PATCH v3 04/17] perf: x86/ds: Handle guest PEBS overflow PMI and inject it to guest Like Xu
2021-01-13 18:22 ` Peter Zijlstra
2021-01-13 18:27 ` Peter Zijlstra
2021-01-14 3:39 ` Xu, Like
2021-01-15 12:01 ` Peter Zijlstra
2021-01-15 14:30 ` Xu, Like
2021-01-15 14:44 ` Peter Zijlstra
2021-01-15 15:12 ` Xu, Like
2021-01-25 8:26 ` Like Xu
2021-01-25 11:47 ` Peter Zijlstra
2021-02-02 6:31 ` Xu, Like
2021-01-14 18:55 ` Sean Christopherson
2021-01-15 2:49 ` Xu, Like
2021-01-15 17:42 ` Sean Christopherson
2021-01-22 5:30 ` Like Xu
2021-01-04 13:15 ` [PATCH v3 05/17] KVM: x86/pmu: Reprogram guest PEBS event to emulate guest PEBS counter Like Xu
2021-01-15 11:33 ` Peter Zijlstra
2021-01-15 13:53 ` Xu, Like
2021-01-04 13:15 ` [PATCH v3 06/17] KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS Like Xu
2021-01-05 21:11 ` Sean Christopherson
2021-01-07 12:38 ` Xu, Like
2021-01-15 14:46 ` Peter Zijlstra
2021-01-15 15:29 ` Xu, Like [this message]
2021-01-04 13:15 ` [PATCH v3 07/17] KVM: x86/pmu: Add IA32_DS_AREA MSR emulation to manage guest DS buffer Like Xu
2021-01-05 21:16 ` Sean Christopherson
2021-01-08 3:05 ` Xu, Like
2021-01-04 13:15 ` [PATCH v3 08/17] KVM: x86/pmu: Add PEBS_DATA_CFG MSR emulation to support adaptive PEBS Like Xu
2021-01-04 13:15 ` [PATCH v3 09/17] KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled Like Xu
2021-01-04 13:15 ` [PATCH v3 10/17] KVM: x86/pmu: Expose CPUIDs feature bits PDCM, DS, DTES64 Like Xu
2021-01-04 13:15 ` [PATCH v3 11/17] KVM: x86/pmu: Adjust precise_ip to emulate Ice Lake guest PDIR counter Like Xu
2021-01-04 13:15 ` [PATCH v3 12/17] KVM: x86/pmu: Disable guest PEBS when counters are cross-mapped Like Xu
2021-01-04 13:15 ` [PATCH v3 13/17] KVM: x86/pmu: Add hook to emulate pebs for cross-mapped counters Like Xu
2021-01-04 13:15 ` [PATCH v3 14/17] KVM: vmx/pmu: Limit pebs_interrupt_threshold in the guest DS area Like Xu
2021-01-04 13:15 ` [PATCH v3 15/17] KVM: vmx/pmu: Rewrite applicable_counters field in guest PEBS records Like Xu
2021-01-04 13:15 ` [PATCH v3 16/17] KVM: x86/pmu: Save guest pebs reset values when pebs is configured Like Xu
2021-01-04 13:15 ` [PATCH v3 17/17] KVM: x86/pmu: Adjust guest pebs reset values for crpss-mapped counters Like Xu
2021-01-14 19:10 ` [PATCH v3 00/17] KVM: x86/pmu: Add support to enable Guest PEBS via DS Sean Christopherson
2021-01-15 2:02 ` Xu, Like
2021-01-15 17:57 ` Sean Christopherson
2021-01-15 18:27 ` Andi Kleen
2021-01-15 18:51 ` Sean Christopherson
2021-01-15 19:11 ` Andi Kleen
2021-01-22 9:56 ` Peter Zijlstra
2021-01-25 8:08 ` Like Xu
2021-01-25 11:13 ` Peter Zijlstra
2021-01-25 12:07 ` Xu, Like
2021-01-25 12:18 ` Peter Zijlstra
2021-01-25 12:53 ` Xu, Like
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