From: Marc Zyngier <marc.zyngier@arm.com>
To: Alexandru Elisei <alexandru.elisei@arm.com>,
linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org
Cc: Andre Przywara <andre.przywara@arm.com>,
Dave Martin <Dave.Martin@arm.com>
Subject: Re: [PATCH 01/59] KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
Date: Wed, 3 Jul 2019 13:32:26 +0100 [thread overview]
Message-ID: <1f37d4d2-9d67-bbb8-0df8-8e239208d746@arm.com> (raw)
In-Reply-To: <1b5c4ba2-dc19-e5ab-d752-7abfdc61daf8@arm.com>
On 24/06/2019 13:59, Alexandru Elisei wrote:
> On 6/21/19 10:37 AM, Marc Zyngier wrote:
>> From: Dave Martin <Dave.Martin@arm.com>
>>
>> Currently, the {read,write}_sysreg_el*() accessors for accessing
>> particular ELs' sysregs in the presence of VHE rely on some local
>> hacks and define their system register encodings in a way that is
>> inconsistent with the core definitions in <asm/sysreg.h>.
>>
>> As a result, it is necessary to add duplicate definitions for any
>> system register that already needs a definition in sysreg.h for
>> other reasons.
>>
>> This is a bit of a maintenance headache, and the reasons for the
>> _el*() accessors working the way they do is a bit historical.
>>
>> This patch gets rid of the shadow sysreg definitions in
>> <asm/kvm_hyp.h>, converts the _el*() accessors to use the core
>> __msr_s/__mrs_s interface, and converts all call sites to use the
>> standard sysreg #define names (i.e., upper case, with SYS_ prefix).
>>
>> This patch will conflict heavily anyway, so the opportunity taken
>> to clean up some bad whitespace in the context of the changes is
>> taken.
>>
>> The change exposes a few system registers that have no sysreg.h
>> definition, due to msr_s/mrs_s being used in place of msr/mrs:
>> additions are made in order to fill in the gaps.
>>
>> Signed-off-by: Dave Martin <Dave.Martin@arm.com>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Christoffer Dall <christoffer.dall@arm.com>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Link: https://www.spinics.net/lists/kvm-arm/msg31717.html
>> [Rebased to v4.21-rc1]
>> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
>> [Rebased to v5.2-rc5, changelog updates]
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>> arch/arm/include/asm/kvm_hyp.h | 13 ++--
>> arch/arm64/include/asm/kvm_emulate.h | 16 ++---
>> arch/arm64/include/asm/kvm_hyp.h | 50 ++-------------
>> arch/arm64/include/asm/sysreg.h | 35 ++++++++++-
>> arch/arm64/kvm/hyp/switch.c | 14 ++---
>> arch/arm64/kvm/hyp/sysreg-sr.c | 78 ++++++++++++------------
>> arch/arm64/kvm/hyp/tlb.c | 12 ++--
>> arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c | 2 +-
>> arch/arm64/kvm/regmap.c | 4 +-
>> arch/arm64/kvm/sys_regs.c | 56 ++++++++---------
>> virt/kvm/arm/arch_timer.c | 24 ++++----
>> 11 files changed, 148 insertions(+), 156 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/kvm_hyp.h b/arch/arm/include/asm/kvm_hyp.h
>> index 87bcd18df8d5..059224fb14db 100644
>> --- a/arch/arm/include/asm/kvm_hyp.h
>> +++ b/arch/arm/include/asm/kvm_hyp.h
>> @@ -93,13 +93,14 @@
>> #define VFP_FPEXC __ACCESS_VFP(FPEXC)
>>
>> /* AArch64 compatibility macros, only for the timer so far */
>> -#define read_sysreg_el0(r) read_sysreg(r##_el0)
>> -#define write_sysreg_el0(v, r) write_sysreg(v, r##_el0)
>> +#define read_sysreg_el0(r) read_sysreg(r##_EL0)
>> +#define write_sysreg_el0(v, r) write_sysreg(v, r##_EL0)
>> +
>> +#define SYS_CNTP_CTL_EL0 CNTP_CTL
>> +#define SYS_CNTP_CVAL_EL0 CNTP_CVAL
>> +#define SYS_CNTV_CTL_EL0 CNTV_CTL
>> +#define SYS_CNTV_CVAL_EL0 CNTV_CVAL
>>
>> -#define cntp_ctl_el0 CNTP_CTL
>> -#define cntp_cval_el0 CNTP_CVAL
>> -#define cntv_ctl_el0 CNTV_CTL
>> -#define cntv_cval_el0 CNTV_CVAL
>> #define cntvoff_el2 CNTVOFF
>> #define cnthctl_el2 CNTHCTL
>>
>> diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
>> index 613427fafff9..39ffe41855bc 100644
>> --- a/arch/arm64/include/asm/kvm_emulate.h
>> +++ b/arch/arm64/include/asm/kvm_emulate.h
>> @@ -137,7 +137,7 @@ static inline unsigned long *__vcpu_elr_el1(const struct kvm_vcpu *vcpu)
>> static inline unsigned long vcpu_read_elr_el1(const struct kvm_vcpu *vcpu)
>> {
>> if (vcpu->arch.sysregs_loaded_on_cpu)
>> - return read_sysreg_el1(elr);
>> + return read_sysreg_el1(SYS_ELR);
>> else
>> return *__vcpu_elr_el1(vcpu);
>> }
>> @@ -145,7 +145,7 @@ static inline unsigned long vcpu_read_elr_el1(const struct kvm_vcpu *vcpu)
>> static inline void vcpu_write_elr_el1(const struct kvm_vcpu *vcpu, unsigned long v)
>> {
>> if (vcpu->arch.sysregs_loaded_on_cpu)
>> - write_sysreg_el1(v, elr);
>> + write_sysreg_el1(v, SYS_ELR);
>> else
>> *__vcpu_elr_el1(vcpu) = v;
>> }
>> @@ -197,7 +197,7 @@ static inline unsigned long vcpu_read_spsr(const struct kvm_vcpu *vcpu)
>> return vcpu_read_spsr32(vcpu);
>>
>> if (vcpu->arch.sysregs_loaded_on_cpu)
>> - return read_sysreg_el1(spsr);
>> + return read_sysreg_el1(SYS_SPSR);
>> else
>> return vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
>> }
>> @@ -210,7 +210,7 @@ static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v)
>> }
>>
>> if (vcpu->arch.sysregs_loaded_on_cpu)
>> - write_sysreg_el1(v, spsr);
>> + write_sysreg_el1(v, SYS_SPSR);
>> else
>> vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v;
>> }
>> @@ -462,13 +462,13 @@ static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
>> */
>> static inline void __hyp_text __kvm_skip_instr(struct kvm_vcpu *vcpu)
>> {
>> - *vcpu_pc(vcpu) = read_sysreg_el2(elr);
>> - vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(spsr);
>> + *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
>> + vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(SYS_SPSR);
>>
>> kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
>>
>> - write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, spsr);
>> - write_sysreg_el2(*vcpu_pc(vcpu), elr);
>> + write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, SYS_SPSR);
>> + write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
>> }
>>
>> #endif /* __ARM64_KVM_EMULATE_H__ */
>> diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h
>> index 09fe8bd15f6e..ce99c2daff04 100644
>> --- a/arch/arm64/include/asm/kvm_hyp.h
>> +++ b/arch/arm64/include/asm/kvm_hyp.h
>> @@ -29,7 +29,7 @@
>> #define read_sysreg_elx(r,nvh,vh) \
>> ({ \
>> u64 reg; \
>> - asm volatile(ALTERNATIVE("mrs %0, " __stringify(r##nvh),\
>> + asm volatile(ALTERNATIVE(__mrs_s("%0", r##nvh), \
>> __mrs_s("%0", r##vh), \
>> ARM64_HAS_VIRT_HOST_EXTN) \
>> : "=r" (reg)); \
>> @@ -39,7 +39,7 @@
>> #define write_sysreg_elx(v,r,nvh,vh) \
>> do { \
>> u64 __val = (u64)(v); \
>> - asm volatile(ALTERNATIVE("msr " __stringify(r##nvh) ", %x0",\
>> + asm volatile(ALTERNATIVE(__msr_s(r##nvh, "%x0"), \
>> __msr_s(r##vh, "%x0"), \
>> ARM64_HAS_VIRT_HOST_EXTN) \
>> : : "rZ" (__val)); \
>> @@ -48,55 +48,15 @@
>> /*
>> * Unified accessors for registers that have a different encoding
>> * between VHE and non-VHE. They must be specified without their "ELx"
>> - * encoding.
>> + * encoding, but with the SYS_ prefix, as defined in asm/sysreg.h.
>> */
>> -#define read_sysreg_el2(r) \
>> - ({ \
>> - u64 reg; \
>> - asm volatile(ALTERNATIVE("mrs %0, " __stringify(r##_EL2),\
>> - "mrs %0, " __stringify(r##_EL1),\
>> - ARM64_HAS_VIRT_HOST_EXTN) \
>> - : "=r" (reg)); \
>> - reg; \
>> - })
>> -
>> -#define write_sysreg_el2(v,r) \
>> - do { \
>> - u64 __val = (u64)(v); \
>> - asm volatile(ALTERNATIVE("msr " __stringify(r##_EL2) ", %x0",\
>> - "msr " __stringify(r##_EL1) ", %x0",\
>> - ARM64_HAS_VIRT_HOST_EXTN) \
>> - : : "rZ" (__val)); \
>> - } while (0)
>>
>> #define read_sysreg_el0(r) read_sysreg_elx(r, _EL0, _EL02)
>> #define write_sysreg_el0(v,r) write_sysreg_elx(v, r, _EL0, _EL02)
>> #define read_sysreg_el1(r) read_sysreg_elx(r, _EL1, _EL12)
>> #define write_sysreg_el1(v,r) write_sysreg_elx(v, r, _EL1, _EL12)
>> -
>> -/* The VHE specific system registers and their encoding */
>> -#define sctlr_EL12 sys_reg(3, 5, 1, 0, 0)
>> -#define cpacr_EL12 sys_reg(3, 5, 1, 0, 2)
>> -#define ttbr0_EL12 sys_reg(3, 5, 2, 0, 0)
>> -#define ttbr1_EL12 sys_reg(3, 5, 2, 0, 1)
>> -#define tcr_EL12 sys_reg(3, 5, 2, 0, 2)
>> -#define afsr0_EL12 sys_reg(3, 5, 5, 1, 0)
>> -#define afsr1_EL12 sys_reg(3, 5, 5, 1, 1)
>> -#define esr_EL12 sys_reg(3, 5, 5, 2, 0)
>> -#define far_EL12 sys_reg(3, 5, 6, 0, 0)
>> -#define mair_EL12 sys_reg(3, 5, 10, 2, 0)
>> -#define amair_EL12 sys_reg(3, 5, 10, 3, 0)
>> -#define vbar_EL12 sys_reg(3, 5, 12, 0, 0)
>> -#define contextidr_EL12 sys_reg(3, 5, 13, 0, 1)
>> -#define cntkctl_EL12 sys_reg(3, 5, 14, 1, 0)
>> -#define cntp_tval_EL02 sys_reg(3, 5, 14, 2, 0)
>> -#define cntp_ctl_EL02 sys_reg(3, 5, 14, 2, 1)
>> -#define cntp_cval_EL02 sys_reg(3, 5, 14, 2, 2)
>> -#define cntv_tval_EL02 sys_reg(3, 5, 14, 3, 0)
>> -#define cntv_ctl_EL02 sys_reg(3, 5, 14, 3, 1)
>> -#define cntv_cval_EL02 sys_reg(3, 5, 14, 3, 2)
>> -#define spsr_EL12 sys_reg(3, 5, 4, 0, 0)
>> -#define elr_EL12 sys_reg(3, 5, 4, 0, 1)
>> +#define read_sysreg_el2(r) read_sysreg_elx(r, _EL2, _EL1)
>> +#define write_sysreg_el2(v,r) write_sysreg_elx(v, r, _EL2, _EL1)
>>
>> /**
>> * hyp_alternate_select - Generates patchable code sequences that are
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 902d75b60914..434cf53d527b 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -202,6 +202,9 @@
>> #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
>> #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
>>
>> +#define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
>> +#define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
>> +
>> #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
>>
>> #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
>> @@ -393,6 +396,9 @@
>> #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
>> #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
>>
>> +#define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
>> +#define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
>> +
>> #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
>> #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
>> #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
>> @@ -403,14 +409,17 @@
>> #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
>> #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
>>
>> -#define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7)
>> +#define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
>>
>> #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
>> -
>> #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
>> +#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
>> +#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
>> #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
>> +#define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
>> #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
>> #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
>> +#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
>>
>> #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
>> #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
>> @@ -455,7 +464,29 @@
>> #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
>>
>> /* VHE encodings for architectural EL0/1 system registers */
>> +#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
>> +#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
>> #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
>> +#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
>> +#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
>> +#define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
>> +#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
>> +#define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
>> +#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
>> +#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
>> +#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
>> +#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
>> +#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
>> +#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
>> +#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
>> +#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
>> +#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
>> +#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
>> +#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
>> +#define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
>> +#define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
>> +#define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
>> +#define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
>>
>> /* Common SCTLR_ELx flags. */
>> #define SCTLR_ELx_DSSBS (_BITUL(44))
>> diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
>> index 8799e0c267d4..7b55c11b30fb 100644
>> --- a/arch/arm64/kvm/hyp/switch.c
>> +++ b/arch/arm64/kvm/hyp/switch.c
>> @@ -295,7 +295,7 @@ static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
>> if (ec != ESR_ELx_EC_DABT_LOW && ec != ESR_ELx_EC_IABT_LOW)
>> return true;
>>
>> - far = read_sysreg_el2(far);
>> + far = read_sysreg_el2(SYS_FAR);
>>
>> /*
>> * The HPFAR can be invalid if the stage 2 fault did not
>> @@ -412,7 +412,7 @@ static bool __hyp_text __hyp_handle_fpsimd(struct kvm_vcpu *vcpu)
>> static bool __hyp_text fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
>> {
>> if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
>> - vcpu->arch.fault.esr_el2 = read_sysreg_el2(esr);
>> + vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
>>
>> /*
>> * We're using the raw exception code in order to only process
>> @@ -708,8 +708,8 @@ static void __hyp_text __hyp_call_panic_nvhe(u64 spsr, u64 elr, u64 par,
>> asm volatile("ldr %0, =__hyp_panic_string" : "=r" (str_va));
>>
>> __hyp_do_panic(str_va,
>> - spsr, elr,
>> - read_sysreg(esr_el2), read_sysreg_el2(far),
>> + spsr, elr,
>> + read_sysreg(esr_el2), read_sysreg_el2(SYS_FAR),
> Seems to me we are pretty sure here we don't have VHE, so why not make both
> reads either read_sysreg or read_sysreg_el2 for consistency? Am I missing something?
You're not missing much, only that it isn't what this change is about.
If we want to make these things consistent, I'd rather have a separate
patch that changes just that.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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next prev parent reply other threads:[~2019-07-03 12:32 UTC|newest]
Thread overview: 179+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-21 9:37 [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support Marc Zyngier
2019-06-21 9:37 ` [PATCH 01/59] KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s Marc Zyngier
2019-06-24 11:16 ` Dave Martin
2019-06-24 12:59 ` Alexandru Elisei
2019-07-03 12:32 ` Marc Zyngier [this message]
2019-06-21 9:37 ` [PATCH 02/59] KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h Marc Zyngier
2019-06-24 11:19 ` Dave Martin
2019-07-03 9:30 ` Marc Zyngier
2019-07-03 16:13 ` Dave Martin
2019-06-21 9:37 ` [PATCH 03/59] arm64: Add ARM64_HAS_NESTED_VIRT cpufeature Marc Zyngier
2019-06-21 13:08 ` Julien Thierry
2019-06-21 13:22 ` Marc Zyngier
2019-06-21 13:44 ` Suzuki K Poulose
2019-06-24 11:24 ` Dave Martin
2019-06-21 9:37 ` [PATCH 04/59] KVM: arm64: nv: Introduce nested virtualization VCPU feature Marc Zyngier
2019-06-21 13:08 ` Julien Thierry
2019-06-24 11:28 ` Dave Martin
2019-07-03 11:53 ` Marc Zyngier
2019-07-03 16:27 ` Dave Martin
2019-06-24 11:43 ` Dave Martin
2019-07-03 11:56 ` Marc Zyngier
2019-07-03 16:24 ` Dave Martin
2019-06-21 9:37 ` [PATCH 05/59] KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set Marc Zyngier
2019-06-24 10:19 ` Suzuki K Poulose
2019-06-24 11:38 ` Dave Martin
2019-06-21 9:37 ` [PATCH 06/59] KVM: arm64: nv: Allow userspace to set PSR_MODE_EL2x Marc Zyngier
2019-06-21 13:24 ` Julien Thierry
2019-06-21 13:50 ` Marc Zyngier
2019-06-24 12:48 ` Dave Martin
2019-07-03 9:21 ` Marc Zyngier
2019-07-04 10:00 ` Dave Martin
2019-06-21 9:37 ` [PATCH 07/59] KVM: arm64: nv: Add EL2 system registers to vcpu context Marc Zyngier
2019-06-24 12:54 ` Dave Martin
2019-07-03 12:20 ` Marc Zyngier
2019-07-03 16:31 ` Dave Martin
2019-06-24 15:47 ` Alexandru Elisei
2019-07-03 13:20 ` Marc Zyngier
2019-07-03 16:01 ` Marc Zyngier
2019-07-01 16:36 ` Suzuki K Poulose
2019-06-21 9:37 ` [PATCH 08/59] KVM: arm64: nv: Reset VMPIDR_EL2 and VPIDR_EL2 to sane values Marc Zyngier
2019-06-24 12:59 ` Dave Martin
2019-06-21 9:37 ` [PATCH 09/59] KVM: arm64: nv: Add nested virt VCPU primitives for vEL2 VCPU state Marc Zyngier
2019-06-24 13:08 ` Dave Martin
2019-06-21 9:37 ` [PATCH 10/59] KVM: arm64: nv: Support virtual EL2 exceptions Marc Zyngier
2019-07-08 13:56 ` Steven Price
2019-06-21 9:37 ` [PATCH 11/59] KVM: arm64: nv: Inject HVC exceptions to the virtual EL2 Marc Zyngier
2019-06-25 13:13 ` Alexandru Elisei
2019-07-03 14:16 ` Marc Zyngier
2019-07-30 14:08 ` Alexandru Elisei
2019-06-21 9:37 ` [PATCH 12/59] KVM: arm64: nv: Handle trapped ERET from " Marc Zyngier
2019-07-02 12:00 ` Alexandru Elisei
2019-06-21 9:37 ` [PATCH 13/59] KVM: arm64: nv: Handle virtual EL2 registers in vcpu_read/write_sys_reg() Marc Zyngier
2019-06-24 12:42 ` Julien Thierry
2019-06-25 14:02 ` Alexandru Elisei
2019-07-03 12:15 ` Marc Zyngier
2019-07-03 15:21 ` Julien Thierry
2019-06-25 15:18 ` Alexandru Elisei
2019-07-01 9:58 ` Alexandru Elisei
2019-07-03 15:59 ` Marc Zyngier
2019-07-03 16:32 ` Alexandru Elisei
2019-07-04 14:39 ` Marc Zyngier
2019-06-26 15:04 ` Alexandru Elisei
2019-07-04 15:05 ` Marc Zyngier
2019-07-01 12:10 ` Alexandru Elisei
2019-06-21 9:37 ` [PATCH 14/59] KVM: arm64: nv: Handle SPSR_EL2 specially Marc Zyngier
2019-06-21 9:37 ` [PATCH 15/59] KVM: arm64: nv: Refactor vcpu_{read,write}_sys_reg Marc Zyngier
2019-06-24 15:07 ` Julien Thierry
2019-07-03 13:09 ` Marc Zyngier
2019-06-27 9:21 ` Alexandru Elisei
2019-07-04 15:15 ` Marc Zyngier
2019-06-21 9:38 ` [PATCH 16/59] KVM: arm64: nv: Save/Restore vEL2 sysregs Marc Zyngier
2019-06-25 8:48 ` Julien Thierry
2019-07-03 13:42 ` Marc Zyngier
2019-07-01 12:09 ` Alexandru Elisei
2019-08-21 11:57 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 17/59] KVM: arm64: nv: Emulate PSTATE.M for a guest hypervisor Marc Zyngier
2019-06-21 9:38 ` [PATCH 18/59] KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2 Marc Zyngier
2019-07-01 16:12 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 19/59] KVM: arm64: nv: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from " Marc Zyngier
2019-06-21 9:38 ` [PATCH 20/59] KVM: arm64: nv: Trap CPACR_EL1 access in " Marc Zyngier
2019-07-01 16:40 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 21/59] KVM: arm64: nv: Set a handler for the system instruction traps Marc Zyngier
2019-06-25 12:55 ` Julien Thierry
2019-07-03 14:15 ` Marc Zyngier
2019-06-21 9:38 ` [PATCH 22/59] KVM: arm64: nv: Handle PSCI call via smc from the guest Marc Zyngier
2019-06-21 9:38 ` [PATCH 23/59] KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting Marc Zyngier
2019-06-25 14:19 ` Julien Thierry
2019-07-02 12:54 ` Alexandru Elisei
2019-07-03 14:18 ` Marc Zyngier
2019-06-21 9:38 ` [PATCH 24/59] KVM: arm64: nv: Respect virtual CPTR_EL2.TFP setting Marc Zyngier
2019-06-21 9:38 ` [PATCH 25/59] KVM: arm64: nv: Don't expose SVE to nested guests Marc Zyngier
2019-06-21 9:38 ` [PATCH 26/59] KVM: arm64: nv: Respect the virtual HCR_EL2.NV bit setting Marc Zyngier
2019-06-26 5:31 ` Julien Thierry
2019-07-03 16:31 ` Marc Zyngier
2019-06-21 9:38 ` [PATCH 27/59] KVM: arm64: nv: Respect virtual HCR_EL2.TVM and TRVM settings Marc Zyngier
2019-06-26 6:55 ` Julien Thierry
2019-07-04 14:57 ` Marc Zyngier
2019-06-21 9:38 ` [PATCH 28/59] KVM: arm64: nv: Respect the virtual HCR_EL2.NV1 bit setting Marc Zyngier
2019-06-26 7:23 ` Julien Thierry
2019-07-02 16:32 ` Alexandru Elisei
2019-07-03 9:10 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 29/59] KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2 Marc Zyngier
2019-07-03 9:16 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 30/59] KVM: arm64: nv: Configure HCR_EL2 for nested virtualization Marc Zyngier
2019-06-21 9:38 ` [PATCH 31/59] KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2 changes Marc Zyngier
2019-06-21 9:38 ` [PATCH 32/59] KVM: arm64: nv: Hide RAS from nested guests Marc Zyngier
2019-07-03 13:59 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 33/59] KVM: arm64: nv: Pretend we only support larger-than-host page sizes Marc Zyngier
2019-07-03 14:13 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 34/59] KVM: arm/arm64: nv: Factor out stage 2 page table data from struct kvm Marc Zyngier
2019-07-03 15:52 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 35/59] KVM: arm/arm64: nv: Support multiple nested stage 2 mmu structures Marc Zyngier
2019-06-25 12:19 ` Alexandru Elisei
2019-07-03 13:47 ` Marc Zyngier
2019-06-27 13:15 ` Julien Thierry
2019-07-04 15:51 ` Alexandru Elisei
2020-01-05 11:35 ` Marc Zyngier
2020-01-06 16:31 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 36/59] KVM: arm64: nv: Implement nested Stage-2 page table walk logic Marc Zyngier
2019-06-21 9:38 ` [PATCH 37/59] KVM: arm64: nv: Handle shadow stage 2 page faults Marc Zyngier
2019-07-05 14:28 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 38/59] KVM: arm64: nv: Unmap/flush shadow stage 2 page tables Marc Zyngier
2019-07-01 8:03 ` Julien Thierry
2019-06-21 9:38 ` [PATCH 39/59] KVM: arm64: nv: Move last_vcpu_ran to be per s2 mmu Marc Zyngier
2019-07-01 9:10 ` Julien Thierry
2019-07-05 15:28 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 40/59] KVM: arm64: nv: Don't always start an S2 MMU search from the beginning Marc Zyngier
2019-07-09 9:59 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 41/59] KVM: arm64: nv: Introduce sys_reg_desc.forward_trap Marc Zyngier
2019-06-21 9:38 ` [PATCH 42/59] KVM: arm64: nv: Rework the system instruction emulation framework Marc Zyngier
2019-06-21 9:38 ` [PATCH 43/59] KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2 Marc Zyngier
2019-07-01 15:45 ` Julien Thierry
2019-07-09 13:20 ` Alexandru Elisei
2019-07-18 12:13 ` Tomasz Nowicki
2019-07-18 12:36 ` Alexandru Elisei
2019-07-18 12:56 ` Alexandru Elisei
2019-07-18 12:59 ` Tomasz Nowicki
2019-07-24 10:25 ` Tomasz Nowicki
2019-07-24 12:39 ` Marc Zyngier
2019-07-24 13:56 ` Tomasz Nowicki
2019-06-21 9:38 ` [PATCH 44/59] KVM: arm64: nv: Trap and emulate TLBI " Marc Zyngier
2019-07-02 12:37 ` Julien Thierry
2019-07-10 10:15 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 45/59] KVM: arm64: nv: Handle traps for timer _EL02 and _EL2 sysregs accessors Marc Zyngier
2019-06-21 9:38 ` [PATCH 46/59] KVM: arm64: nv: arch_timer: Support hyp timer emulation Marc Zyngier
2019-07-10 16:23 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 47/59] KVM: arm64: nv: Propagate CNTVOFF_EL2 to the virtual EL1 timer Marc Zyngier
2019-08-08 9:34 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 48/59] KVM: arm64: nv: Load timer before the GIC Marc Zyngier
2019-07-11 13:17 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 49/59] KVM: arm64: nv: vgic-v3: Take cpu_if pointer directly instead of vcpu Marc Zyngier
2019-06-21 9:38 ` [PATCH 50/59] KVM: arm64: nv: Nested GICv3 Support Marc Zyngier
2019-07-16 11:41 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 51/59] KVM: arm64: nv: vgic: Emulate the HW bit in software Marc Zyngier
2019-06-21 9:38 ` [PATCH 52/59] KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ Marc Zyngier
2019-07-04 7:38 ` Julien Thierry
2019-07-04 9:01 ` Andre Przywara
2019-07-04 9:04 ` Julien Thierry
2019-06-21 9:38 ` [PATCH 53/59] KVM: arm64: nv: Implement maintenance interrupt forwarding Marc Zyngier
2019-07-04 8:06 ` Julien Thierry
2019-07-16 16:35 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 54/59] KVM: arm64: nv: Add nested GICv3 tracepoints Marc Zyngier
2019-06-21 9:38 ` [PATCH 55/59] arm64: KVM: nv: Add handling of EL2-specific timer registers Marc Zyngier
2019-07-11 12:35 ` Alexandru Elisei
2019-07-17 10:19 ` Alexandru Elisei
2019-06-21 9:38 ` [PATCH 56/59] arm64: KVM: nv: Honor SCTLR_EL2.SPAN on entering vEL2 Marc Zyngier
2019-06-21 9:38 ` [PATCH 57/59] arm64: KVM: nv: Handle SCTLR_EL2 RES0/RES1 bits Marc Zyngier
2019-06-21 9:38 ` [PATCH 58/59] arm64: KVM: nv: Restrict S2 RD/WR permissions to match the guest's Marc Zyngier
2019-06-21 9:38 ` [PATCH 59/59] arm64: KVM: nv: Allow userspace to request KVM_ARM_VCPU_NESTED_VIRT Marc Zyngier
2019-06-21 9:57 ` [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support Itaru Kitayama
2019-06-21 11:21 ` Marc Zyngier
2019-08-02 10:11 ` Alexandru Elisei
2019-08-02 10:30 ` Andrew Jones
2019-08-09 10:01 ` Alexandru Elisei
2019-08-09 11:44 ` Andrew Jones
2019-08-09 12:00 ` Alexandru Elisei
2019-08-09 13:00 ` Andrew Jones
2019-08-22 11:57 ` Alexandru Elisei
2019-08-22 15:32 ` Alexandru Elisei
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