From: Andrew Murray <andrew.murray@arm.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v8 5/6] KVM: arm/arm64: remove pmc->bitmask
Date: Wed, 22 May 2019 17:26:08 +0100 [thread overview]
Message-ID: <20190522162608.GF8268@e119886-lin.cambridge.arm.com> (raw)
In-Reply-To: <7f84fcac-ee73-d076-f0e3-3b214912daaf@arm.com>
On Wed, May 22, 2019 at 05:07:31PM +0100, Marc Zyngier wrote:
> On 22/05/2019 16:30, Andrew Murray wrote:
> > We currently use pmc->bitmask to determine the width of the pmc - however
> > it's superfluous as the pmc index already describes if the pmc is a cycle
> > counter or event counter. The architecture clearly describes the widths of
> > these counters.
> >
> > Let's remove the bitmask to simplify the code.
> >
> > Signed-off-by: Andrew Murray <andrew.murray@arm.com>
> > ---
> > include/kvm/arm_pmu.h | 1 -
> > virt/kvm/arm/pmu.c | 15 +++++----------
> > 2 files changed, 5 insertions(+), 11 deletions(-)
> >
> > diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
> > index b73f31baca52..2f0e28dc5a9e 100644
> > --- a/include/kvm/arm_pmu.h
> > +++ b/include/kvm/arm_pmu.h
> > @@ -28,7 +28,6 @@
> > struct kvm_pmc {
> > u8 idx; /* index into the pmu->pmc array */
> > struct perf_event *perf_event;
> > - u64 bitmask;
> > };
> >
> > struct kvm_pmu {
> > diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
> > index ae1e886d4a1a..c4e2bc213617 100644
> > --- a/virt/kvm/arm/pmu.c
> > +++ b/virt/kvm/arm/pmu.c
> > @@ -47,7 +47,10 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
> > counter += perf_event_read_value(pmc->perf_event, &enabled,
> > &running);
> >
> > - return counter & pmc->bitmask;
> > + if (select_idx != ARMV8_PMU_CYCLE_IDX)
> > + counter = lower_32_bits(counter);
> > +
> > + return counter;
> > }
> >
> > /**
> > @@ -113,7 +116,6 @@ void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu)
> > for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) {
> > kvm_pmu_stop_counter(vcpu, &pmu->pmc[i]);
> > pmu->pmc[i].idx = i;
> > - pmu->pmc[i].bitmask = 0xffffffffUL;
> > }
> > }
> >
> > @@ -348,8 +350,6 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val)
> > */
> > void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
> > {
> > - struct kvm_pmu *pmu = &vcpu->arch.pmu;
> > - struct kvm_pmc *pmc;
> > u64 mask;
> > int i;
> >
> > @@ -368,11 +368,6 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
> > for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++)
> > kvm_pmu_set_counter_value(vcpu, i, 0);
> > }
> > -
> > - if (val & ARMV8_PMU_PMCR_LC) {
> > - pmc = &pmu->pmc[ARMV8_PMU_CYCLE_IDX];
> > - pmc->bitmask = 0xffffffffffffffffUL;
> > - }
> > }
> >
> > static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u64 select_idx)
> > @@ -420,7 +415,7 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx)
> >
> > counter = kvm_pmu_get_counter_value(vcpu, select_idx);
> > /* The initial sample period (overflow count) of an event. */
> > - attr.sample_period = (-counter) & pmc->bitmask;
> > + attr.sample_period = (-counter) & GENMASK(31, 0);
>
> Isn't this the one case where the bitmask actually matters? If we're
> dealing with the cycle counter, it shouldn't be truncated, right?
Ah yes, that should be conditional on idx as well.
Thanks,
Andrew Murray
>
> >
> > event = perf_event_create_kernel_counter(&attr, -1, current,
> > kvm_pmu_perf_overflow, pmc);
> >
>
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny...
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2019-05-22 16:26 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-22 15:30 [PATCH v8 0/6] KVM: arm/arm64: add support for chained counters Andrew Murray
2019-05-22 15:30 ` [PATCH v8 1/6] KVM: arm/arm64: rename kvm_pmu_{enable/disable}_counter functions Andrew Murray
2019-05-22 15:30 ` [PATCH v8 2/6] KVM: arm/arm64: extract duplicated code to own function Andrew Murray
2019-05-22 15:30 ` [PATCH v8 3/6] KVM: arm/arm64: re-create event when setting counter value Andrew Murray
2019-05-22 15:30 ` [PATCH v8 4/6] arm64: perf: extract chain helper into header Andrew Murray
2019-06-10 11:39 ` Will Deacon
2019-05-22 15:30 ` [PATCH v8 5/6] KVM: arm/arm64: remove pmc->bitmask Andrew Murray
2019-05-22 16:07 ` Marc Zyngier
2019-05-22 16:26 ` Andrew Murray [this message]
2019-06-10 12:54 ` Suzuki K Poulose
2019-06-12 14:30 ` Andrew Murray
2019-05-22 15:30 ` [PATCH v8 6/6] KVM: arm/arm64: support chained PMU counters Andrew Murray
2019-06-10 10:21 ` Julien Thierry
2019-06-10 16:05 ` Suzuki K Poulose
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190522162608.GF8268@e119886-lin.cambridge.arm.com \
--to=andrew.murray@arm.com \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=marc.zyngier@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).