From: Will Deacon <will@kernel.org>
To: Marc Zyngier <maz@kernel.org>
Cc: kernel-team@android.com, kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 6/7] KVM: arm64: Handle stage-2 faults on stage-1 page-table walks earlier
Date: Mon, 27 Jul 2020 11:29:57 +0100 [thread overview]
Message-ID: <20200727102957.GA20194@willie-the-truck> (raw)
In-Reply-To: <87r1sywg4h.wl-maz@kernel.org>
On Sun, Jul 26, 2020 at 02:38:38PM +0100, Marc Zyngier wrote:
> On Fri, 24 Jul 2020 15:35:05 +0100,
> Will Deacon <will@kernel.org> wrote:
> >
> > Stage-2 faults on stage-1 page-table walks can occur on both the I-side
> > and the D-side. It is IMPLEMENTATATION DEFINED whether they are reported
> > as reads or writes and, in the case that they are generated by an AT
> > instruction, they are reported with the CM bit set.
> >
> > All of this deeply confuses the logic in kvm_handle_guest_abort();
> > userspace may or may not see the fault, depending on whether it occurs
> > on the data or the instruction side, and an AT instruction may be skipped
> > if the translation tables are held in a read-only memslot.
>
> Yuk, that's indeed ugly. Well spotted. I guess the saving grace is
> that a S2 trap caused by an ATS1 instruction will be reported as
> S1PTW+CM, while the fault caused by a CMO is reported as *either*
> S1PTW *or* CM, but never both.
Hmm, is that right? If the translation faults at S2 for a CM instruction,
wouldn't it have both bits set?
> > Move the handling of stage-2 faults on stage-1 page-table walks earlier
> > so that they consistently result in either a data or an instruction abort
> > being re-injected back to the guest.
>
> The instruction abort seems to be happening as the side effect of
> executing outside of a memslot, not really because of a S1PTW.
Not sure about that. If the instruction fetch generates an S2 abort during
translation, then we could be executing from within a memslot; it's the
location of the page-tables that matters.
However, I think that means things still aren't quite right with my patches
because we can end up calling io_mem_abort() from an instruction abort,
which won't have enough syndrome information to do anything useful. Hmm.
Stepping back, here's what I _think_ we want, although see the '(?)'
bits where I'm particularly unsure:
S2 instruction abort:
* Not in memslot: inject external iabt to guest
* In R/O memslot:
- S2 fault on S1 walk: either EXIT_NISV or inject external iabt
to guest (?)
S2 data abort:
* Not in memslot:
- S2 fault on S1 walk: inject external dabt to guest
- Cache maintenance: skip instr
- Syndrome valid EXIT_MMIO
- Syndrome invalid EXIT_NISV
* In R/O memslot:
- S2 fault on S1 walk: either EXIT_NISV or inject external dabt
to guest (?)
- Access is write (including cache maintenance (?)):
- Syndrome valid EXIT_MMIO
- Syndrome invalid EXIT_NISV
Everything else gets handled by handle_access_fault()/user_mem_abort().
What do you think?
> I wonder whether these S1PTW faults should be classified as external
> aborts instead (because putting your page tables outside of a memslot
> seems a bit bonkers).
I think that's what this patch does, since we end up in kvm_inject_dabt().
Will
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2020-07-27 10:30 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-24 14:34 [PATCH 0/7] KVM: arm64: Fixes to early stage-2 fault handling Will Deacon
2020-07-24 14:35 ` [PATCH 1/7] KVM: arm64: Update comment when skipping guest MMIO access instruction Will Deacon
2020-07-26 11:08 ` Marc Zyngier
2020-07-27 10:30 ` Will Deacon
2020-07-24 14:35 ` [PATCH 2/7] KVM: arm64: Rename kvm_vcpu_dabt_isextabt() Will Deacon
2020-07-26 11:15 ` Marc Zyngier
2020-07-27 10:30 ` Will Deacon
2020-07-24 14:35 ` [PATCH 3/7] KVM: arm64: Handle data and instruction external aborts the same way Will Deacon
2020-07-24 14:35 ` [PATCH 4/7] KVM: arm64: Remove useless local variable Will Deacon
2020-07-24 14:35 ` [PATCH 5/7] KVM: arm64: Move 'invalid syndrome' logic out of io_mem_abort() Will Deacon
2020-07-26 11:55 ` Marc Zyngier
2020-07-27 10:31 ` Will Deacon
2020-07-24 14:35 ` [PATCH 6/7] KVM: arm64: Handle stage-2 faults on stage-1 page-table walks earlier Will Deacon
2020-07-26 13:38 ` Marc Zyngier
2020-07-27 10:29 ` Will Deacon [this message]
2020-07-24 14:35 ` [PATCH 7/7] KVM: arm64: Separate write faults on read-only memslots from MMIO Will Deacon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200727102957.GA20194@willie-the-truck \
--to=will@kernel.org \
--cc=kernel-team@android.com \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=maz@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).