From: Robin Murphy <robin.murphy@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH 1/2] KVM: arm64: Add PMU event filtering infrastructure
Date: Mon, 17 Feb 2020 15:33:21 +0000 [thread overview]
Message-ID: <5d7a2907-f12c-0add-c020-c927aad50feb@arm.com> (raw)
In-Reply-To: <868sl46t60.wl-maz@kernel.org>
On 15/02/2020 10:28 am, Marc Zyngier wrote:
> On Fri, 14 Feb 2020 22:01:01 +0000,
> Robin Murphy <robin.murphy@arm.com> wrote:
>
> Hi Robin,
>
>>
>> Hi Marc,
>>
>> On 2020-02-14 6:36 pm, Marc Zyngier wrote:
>> [...]
>>> @@ -585,6 +585,14 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx)
>>> pmc->idx != ARMV8_PMU_CYCLE_IDX)
>>> return;
>>> + /*
>>> + * If we have a filter in place and that the event isn't allowed, do
>>> + * not install a perf event either.
>>> + */
>>> + if (vcpu->kvm->arch.pmu_filter &&
>>> + !test_bit(eventsel, vcpu->kvm->arch.pmu_filter))
>>> + return;
>>
>> If I'm reading the derivation of eventsel right, this will end up
>> treating cycle counter events (aliased to SW_INCR) differently from
>> CPU_CYCLES, which doesn't seem desirable.
>
> Indeed, this doesn't look quite right.
>
> Looking at the description of event 0x11, it doesn't seem to count
> exactly like the cycle counter (there are a number of PMCR controls
> affecting it). But none of these actually apply to our PMU emulation
> (no secure mode, and the idea of dealing with virtual EL2 in the
> context of the PMU is... not appealing).
>
> Now, given that we implement the cycle counter with event 0x11 anyway,
> I don't think there is any reason to deal with them separately.
Right, from the user's PoV they can only ask for event 0x11, and where
it gets scheduled is more of a black-box implementation detail. Reading
the Arm ARM doesn't leave me entirely convinced that cycles couldn't
ever leak idle/not-idle information between closely-coupled PEs, so this
might not be entirely academic.
>> Also, if the user did try to blacklist SW_INCR for ridiculous
>> reasons, we'd need to special-case kvm_pmu_software_increment() to
>> make it (not) work as expected, right?
>
> I thought of that one, and couldn't see a reason to blacklist it
> (after all, the guest could also increment a variable) and send itself
> an interrupt. I'm tempted to simply document that event 0 is never
> filtered.
I'd say you're on even stronger ground simply because KVM's
implementation of SW_INCR doesn't go near the PMU hardware at all, thus
is well beyond the purpose of the blacklist anyway. I believe it's
important that how the code behaves matches expectations, but there's no
harm in changing the latter as appropriate ;)
Cheers,
Robin.
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next prev parent reply other threads:[~2020-02-17 15:33 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-14 18:36 [PATCH 0/2] KVM: arm64: Filtering PMU events Marc Zyngier
2020-02-14 18:36 ` [PATCH 1/2] KVM: arm64: Add PMU event filtering infrastructure Marc Zyngier
2020-02-14 22:01 ` Robin Murphy
2020-02-15 10:28 ` Marc Zyngier
2020-02-17 15:33 ` Robin Murphy [this message]
2020-02-14 18:36 ` [PATCH 2/2] KVM: arm64: Document PMU filtering API Marc Zyngier
2020-02-15 13:00 ` [PATCH 0/2] KVM: arm64: Filtering PMU events Marc Zyngier
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