From: Richard Henderson <richard.henderson@linaro.org>
To: Marc Zyngier <maz@kernel.org>, qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>,
kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH v2 1/5] target/arm: Honor HCR_EL2.TID2 trapping requirements
Date: Mon, 2 Dec 2019 07:10:48 -0800 [thread overview]
Message-ID: <78a7047a-bc8e-0a90-db9c-7f3a0d3d60d8@linaro.org> (raw)
In-Reply-To: <20191201122018.25808-2-maz@kernel.org>
On 12/1/19 12:20 PM, Marc Zyngier wrote:
> HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1,
> CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU
> completely ignores it, making it impossible for hypervisors to
> virtualize the cache hierarchy.
>
> Do the right thing by trapping to EL2 if HCR_EL2.TID2 is set.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> target/arm/helper.c | 31 +++++++++++++++++++++++++++----
> 1 file changed, 27 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2019-12-02 15:10 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-01 12:20 [PATCH v2 0/5] target/arm: More EL2 trapping fixes Marc Zyngier
2019-12-01 12:20 ` [PATCH v2 1/5] target/arm: Honor HCR_EL2.TID2 trapping requirements Marc Zyngier
2019-12-02 13:52 ` Edgar E. Iglesias
2019-12-02 15:10 ` Richard Henderson [this message]
2019-12-01 12:20 ` [PATCH v2 2/5] target/arm: Honor HCR_EL2.TID1 " Marc Zyngier
2019-12-02 15:22 ` Richard Henderson
2019-12-01 12:20 ` [PATCH v2 3/5] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions Marc Zyngier
2019-12-02 15:35 ` Richard Henderson
2019-12-02 16:45 ` Marc Zyngier
2019-12-02 16:56 ` Richard Henderson
2019-12-02 17:15 ` Marc Zyngier
2019-12-06 14:08 ` Peter Maydell
2019-12-06 14:14 ` Marc Zyngier
2019-12-06 17:45 ` Richard Henderson
2019-12-01 12:20 ` [PATCH v2 4/5] target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 Marc Zyngier
2019-12-02 15:52 ` Richard Henderson
2019-12-01 12:20 ` [PATCH v2 5/5] target/arm: Add support for missing Jazelle system registers Marc Zyngier
2019-12-02 14:07 ` Edgar E. Iglesias
2019-12-02 15:57 ` Richard Henderson
2019-12-06 13:56 ` Peter Maydell
2019-12-06 14:13 ` [PATCH v2 0/5] target/arm: More EL2 trapping fixes Peter Maydell
2019-12-06 14:19 ` Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=78a7047a-bc8e-0a90-db9c-7f3a0d3d60d8@linaro.org \
--to=richard.henderson@linaro.org \
--cc=edgar.iglesias@xilinx.com \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=maz@kernel.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).