From: Auger Eric <eric.auger@redhat.com>
To: Will Deacon <will@kernel.org>
Cc: maz@kernel.org, linux-kernel@vger.kernel.org,
kvmarm@lists.cs.columbia.edu, eric.auger.pro@gmail.com
Subject: Re: [RFC 3/3] KVM: arm64: pmu: Enforce PMEVTYPER evtCount size
Date: Thu, 5 Dec 2019 10:37:24 +0100 [thread overview]
Message-ID: <c1a876be-49ab-0b5f-8ddd-1a47bcf89300@redhat.com> (raw)
In-Reply-To: <20191205090232.GC8606@willie-the-truck>
Hi Will,
On 12/5/19 10:02 AM, Will Deacon wrote:
> On Wed, Dec 04, 2019 at 09:44:26PM +0100, Eric Auger wrote:
>> ARMv8.1-PMU supports 16-bit evtCount whereas 8.0 only supports
>> 10 bits.
>>
>> On Seatlle which has an 8.0 PMU implementation, evtCount[15:10]
>> are not read as 0, as expected. Fix that by applying a mask on
>> the selected event that depends on the PMU version.
>
> Are you sure about that? These bits are RES0 in 8.0 afaict, so this would be
> a CPU erratum. Have you checked the SDEN document (I haven't)?
You're right. It is RES0 and not RAZ. My mistake. Please ignore this patch.
Thank you for the feedback.
Eric
>
> Will
>
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prev parent reply other threads:[~2019-12-05 9:37 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-04 20:44 [RFC 0/3] KVM/ARM: Misc PMU fixes Eric Auger
2019-12-04 20:44 ` [RFC 1/3] KVM: arm64: pmu: Don't increment SW_INCR if PMCR.E is unset Eric Auger
2019-12-05 9:54 ` Marc Zyngier
2019-12-06 10:35 ` Andrew Murray
2019-12-04 20:44 ` [RFC 2/3] KVM: arm64: pmu: Fix chained SW_INCR counters Eric Auger
2019-12-05 9:43 ` Marc Zyngier
2019-12-05 14:06 ` Auger Eric
2019-12-05 14:52 ` Marc Zyngier
2019-12-05 19:01 ` Auger Eric
2019-12-06 9:56 ` Auger Eric
2019-12-06 15:48 ` Andrew Murray
2020-01-19 17:58 ` Marc Zyngier
2020-01-20 13:30 ` Auger Eric
2019-12-06 15:21 ` Andrew Murray
2019-12-06 15:35 ` Marc Zyngier
2019-12-06 16:02 ` Andrew Murray
2019-12-04 20:44 ` [RFC 3/3] KVM: arm64: pmu: Enforce PMEVTYPER evtCount size Eric Auger
2019-12-05 9:02 ` Will Deacon
2019-12-05 9:37 ` Auger Eric [this message]
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