From: Jerome Brunet <jbrunet@baylibre.com>
To: Neil Armstrong <narmstrong@baylibre.com>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/3] clk: meson: g12a: fixes for DVFS
Date: Tue, 01 Oct 2019 15:15:54 +0200 [thread overview]
Message-ID: <1jh84sr4hh.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <20190919093627.21245-1-narmstrong@baylibre.com>
On Thu 19 Sep 2019 at 11:36, Neil Armstrong <narmstrong@baylibre.com> wrote:
> This is the first serie of fixes for DVFS support on G12a:
> - Patch 1 fixes a rebase issue where a CLK_SET_RATE_NO_REPARENT
> appeared on the wrong clock and a SET_RATE_PARENT went missing
> - Patch 2 helps CCF use the right clock tree for the sub 1GHz clock range
> - Patch 3 fixes an issue when we enter suspend with a non-SYS_PLL CPU clock,
> leading to a SYS_PLL never enabled again
>
> Neil Armstrong (3):
> clk: meson: g12a: fix cpu clock rate setting
> clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
> clk: meson: clk-pll: always enable a critical PLL when setting the
> rate
>
> drivers/clk/meson/clk-pll.c | 2 +-
> drivers/clk/meson/g12a.c | 13 +++++++++++--
> 2 files changed, 12 insertions(+), 3 deletions(-)
Applied the 2 first fixes. Thx
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prev parent reply other threads:[~2019-10-01 13:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-19 9:36 [PATCH 0/3] clk: meson: g12a: fixes for DVFS Neil Armstrong
2019-09-19 9:36 ` [PATCH 1/3] clk: meson: g12a: fix cpu clock rate setting Neil Armstrong
2019-09-19 9:36 ` [PATCH 2/3] clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes Neil Armstrong
2019-09-19 9:38 ` [PATCH 3/3] clk: meson: clk-pll: always enable a critical PLL when setting the rate Neil Armstrong
2019-09-19 13:01 ` Jerome Brunet
2019-09-19 17:06 ` Stephen Boyd
2019-09-20 8:06 ` Neil Armstrong
2019-09-20 16:52 ` Stephen Boyd
2019-10-01 13:15 ` Jerome Brunet [this message]
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