From: Neil Armstrong <narmstrong@baylibre.com>
To: khilman@baylibre.com, lorenzo.pieralisi@arm.com, kishon@ti.com,
bhelgaas@google.com, andrew.murray@arm.com,
devicetree@vger.kernel.org
Cc: Rob Herring <robh@kernel.org>,
gouwa@khadas.com, Neil Armstrong <narmstrong@baylibre.com>,
linux-pci@vger.kernel.org, nick@khadas.com,
linux-kernel@vger.kernel.org, yue.wang@Amlogic.com,
repk@triplefau.lt, maz@kernel.org,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/6] dt-bindings: pci: amlogic, meson-pcie: Add G12A bindings
Date: Mon, 16 Sep 2019 14:50:17 +0200 [thread overview]
Message-ID: <20190916125022.10754-2-narmstrong@baylibre.com> (raw)
In-Reply-To: <20190916125022.10754-1-narmstrong@baylibre.com>
Add PCIE bindings for the Amlogic G12A SoC, the support is the same
but the PHY is shared with USB3 to control the differential lines.
Thus this adds a phy phandle to control the PHY, and only requires the
MIPI clock for the Amlogic AXG SoC Family.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
index efa2c8b9b85a..84fdc422792e 100644
--- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -9,13 +9,16 @@ Additional properties are described here:
Required properties:
- compatible:
- should contain "amlogic,axg-pcie" to identify the core.
+ should contain :
+ - "amlogic,axg-pcie" for AXG SoC Family
+ - "amlogic,g12a-pcie" for G12A SoC Family
+ to identify the core.
- reg:
should contain the configuration address space.
- reg-names: Must be
- "elbi" External local bus interface registers
- "cfg" Meson specific registers
- - "phy" Meson PCIE PHY registers
+ - "phy" Meson PCIE PHY registers for AXG SoC Family
- "config" PCIe configuration space
- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
- clocks: Must contain an entry for each entry in clock-names.
@@ -23,12 +26,13 @@ Required properties:
- "pclk" PCIe GEN 100M PLL clock
- "port" PCIe_x(A or B) RC clock gate
- "general" PCIe Phy clock
- - "mipi" PCIe_x(A or B) 100M ref clock gate
+ - "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family
- resets: phandle to the reset lines.
- reset-names: must contain "phy" "port" and "apb"
- - "phy" Share PHY reset
+ - "phy" Share PHY reset for AXG SoC Family
- "port" Port A or B reset
- "apb" Share APB reset
+- phys: should contain a phandle to the shared phy for G12A SoC Family
- device_type:
should be "pci". As specified in designware-pcie.txt
--
2.22.0
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next prev parent reply other threads:[~2019-09-16 12:50 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-16 12:50 [PATCH v2 0/6] arm64: dts: meson-g12: add support for PCIe Neil Armstrong
2019-09-16 12:50 ` Neil Armstrong [this message]
2019-09-16 13:46 ` [PATCH v2 1/6] dt-bindings: pci: amlogic,meson-pcie: Add G12A bindings Andrew Murray
2019-09-16 12:50 ` [PATCH v2 2/6] PCI: amlogic: Fix probed clock names Neil Armstrong
2019-09-16 12:50 ` [PATCH v2 3/6] PCI: amlogic: meson: Add support for G12A Neil Armstrong
2019-09-16 13:20 ` Andrew Murray
2019-09-16 12:50 ` [PATCH v2 4/6] phy: meson-g12a-usb3-pcie: Add support for PCIe mode Neil Armstrong
2019-09-16 13:23 ` Andrew Murray
2019-09-16 12:50 ` [PATCH v2 5/6] arm64: dts: meson-g12a: Add PCIe node Neil Armstrong
2019-09-16 13:42 ` Andrew Murray
2019-09-16 12:50 ` [PATCH v2 6/6] arm64: dts: khadas-vim3: add commented support for PCIe Neil Armstrong
2019-09-16 13:45 ` Andrew Murray
2019-09-24 18:59 ` [PATCH v2 0/6] arm64: dts: meson-g12: add " Kevin Hilman
2019-10-15 13:14 ` Lorenzo Pieralisi
2019-10-15 13:38 ` Neil Armstrong
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