From: Jian Hu <jian.hu@amlogic.com>
To: Jerome Brunet <jbrunet@baylibre.com>,
Neil Armstrong <narmstrong@baylibre.com>
Cc: Rob Herring <robh@kernel.org>,
Victor Wan <victor.wan@amlogic.com>,
Jianxin Pan <jianxin.pan@amlogic.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Kevin Hilman <khilman@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
linux-kernel@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>,
Jian Hu <jian.hu@amlogic.com>,
linux-arm-kernel@lists.infradead.org,
Qiufang Dai <qiufang.dai@amlogic.com>,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
Chandle Zou <chandle.zou@amlogic.com>
Subject: [PATCH v3 7/7] arm64: dts: meson: add A1 PLL and periphs clock controller
Date: Fri, 29 Nov 2019 22:46:05 +0800 [thread overview]
Message-ID: <20191129144605.182774-8-jian.hu@amlogic.com> (raw)
In-Reply-To: <20191129144605.182774-1-jian.hu@amlogic.com>
Add A1 PLL and periphs clock controller node, there are parent
clocks in periphs clocks for PLL clocks, and there are parent
clocks in PLL clocks for periphs clocks. They rely on each other.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 26 +++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad049d1d..ba1cb4aa594b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -5,6 +5,8 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/a1-pll-clkc.h>
+#include <dt-bindings/clock/a1-clkc.h>
/ {
compatible = "amlogic,a1";
@@ -74,6 +76,30 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
+ clkc_pll: pll-clock-controller {
+ compatible = "amlogic,a1-pll-clkc";
+ #clock-cells = <1>;
+ reg = <0 0x7c80 0 0x21c>;
+ clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>,
+ <&clkc_periphs CLKID_XTAL_HIFIPLL>;
+ clock-names = "xtal_fixpll", "xtal_hifipll";
+ };
+
+ clkc_periphs: periphs-clock-controller {
+ compatible = "amlogic,a1-periphs-clkc";
+ #clock-cells = <1>;
+ reg = <0 0x800 0 0x104>;
+ clocks = <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_FCLK_DIV3>,
+ <&clkc_pll CLKID_FCLK_DIV5>,
+ <&clkc_pll CLKID_FCLK_DIV7>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&xtal>;
+ clock-names = "fclk_div2", "fclk_div3",
+ "fclk_div5", "fclk_div7",
+ "hifi_pll", "xtal";
+ };
+
uart_AO: serial@1c00 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
--
2.24.0
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next prev parent reply other threads:[~2019-11-29 14:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-29 14:45 [PATCH v3 0/7] add Amlogic A1 clock controller driver Jian Hu
2019-11-29 14:45 ` [PATCH v3 1/7] dt-bindings: clock: meson: add A1 PLL clock controller bindings Jian Hu
2019-11-29 14:46 ` [PATCH v3 2/7] clk: meson: add support for A1 PLL clock ops Jian Hu
2019-11-29 14:46 ` [PATCH v3 3/7] clk: meson: eeclk: refactor eeclk common driver to support A1 Jian Hu
2019-11-29 14:46 ` [PATCH v3 4/7] clk: meson: a1: add support for Amlogic A1 PLL clock driver Jian Hu
2019-11-29 14:46 ` [PATCH v3 5/7] dt-bindings: clock: meson: add A1 peripheral clock controller bindings Jian Hu
2019-11-29 14:46 ` [PATCH v3 6/7] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver Jian Hu
2019-11-29 14:46 ` Jian Hu [this message]
2019-11-29 15:28 ` [PATCH v3 0/7] add Amlogic A1 clock controller driver Jerome Brunet
2019-12-02 6:01 ` Jian Hu
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