From: Remi Pommarel <repk@triplefau.lt>
To: Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Yue Wang <yue.wang@Amlogic.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-pci@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
linux-kernel@vger.kernel.org, Remi Pommarel <repk@triplefau.lt>,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] clk: meson: axg: add pcie pll cml gating
Date: Sun, 8 Dec 2019 22:03:19 +0100 [thread overview]
Message-ID: <20191208210320.15539-2-repk@triplefau.lt> (raw)
In-Reply-To: <20191208210320.15539-1-repk@triplefau.lt>
PCIE_PLL_CML_ENABLE is used to enable or disable pcie clock PAD
output reliably on AXG platforms.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
---
drivers/clk/meson/axg.c | 3 +++
drivers/clk/meson/axg.h | 2 +-
include/dt-bindings/clock/axg-clkc.h | 1 +
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 13fc0006f63d..ac9ab7f75ee8 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -1142,6 +1142,7 @@ static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);
+static MESON_GATE(axg_pcie_pll_cml_enable, HHI_MIPI_CNTL0, 26);
/* Always On (AO) domain gates */
@@ -1246,6 +1247,7 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
[CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
[CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
[CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
+ [CLKID_PCIE_PLL_CML_ENABLE] = &axg_pcie_pll_cml_enable.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -1341,6 +1343,7 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
&axg_hifi_pll_dco,
&axg_pcie_pll_dco,
&axg_pcie_pll_od,
+ &axg_pcie_pll_cml_enable,
};
static const struct meson_eeclkc_data axg_clkc_data = {
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 0431dabac629..d65670d6c607 100644
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -140,7 +140,7 @@
#define CLKID_PCIE_PLL_DCO 89
#define CLKID_PCIE_PLL_OD 90
-#define NR_CLKS 91
+#define NR_CLKS 92
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/axg-clkc.h>
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
index fd1f938c38d1..218a05ff508d 100644
--- a/include/dt-bindings/clock/axg-clkc.h
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -72,5 +72,6 @@
#define CLKID_PCIE_CML_EN1 80
#define CLKID_MIPI_ENABLE 81
#define CLKID_GEN_CLK 84
+#define CLKID_PCIE_PLL_CML_ENABLE 91
#endif /* __AXG_CLKC_H */
--
2.24.0
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next prev parent reply other threads:[~2019-12-08 20:56 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-08 21:03 [PATCH 0/2] PCI: amlogic: Make PCIe working reliably on AXG platforms Remi Pommarel
2019-12-08 21:03 ` Remi Pommarel [this message]
2019-12-08 22:07 ` [PATCH 1/2] clk: meson: axg: add pcie pll cml gating Martin Blumenstingl
2019-12-08 21:03 ` [PATCH 2/2] PCI: amlogic: Use PCIe pll gate when available Remi Pommarel
2019-12-09 11:03 ` Andrew Murray
2019-12-15 11:38 ` Remi Pommarel
2019-12-09 8:32 ` [PATCH 0/2] PCI: amlogic: Make PCIe working reliably on AXG platforms Jerome Brunet
2019-12-15 11:36 ` Remi Pommarel
2019-12-15 20:44 ` Martin Blumenstingl
2019-12-16 8:47 ` Jerome Brunet
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