From: Remi Pommarel <repk@triplefau.lt>
To: Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Kevin Hilman <khilman@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: linux-amlogic@lists.infradead.org,
Remi Pommarel <repk@triplefau.lt>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 1/2] clk: meson: axg: Remove MIPI enable clock gate
Date: Mon, 9 Mar 2020 22:01:56 +0100 [thread overview]
Message-ID: <20200309210157.29860-2-repk@triplefau.lt> (raw)
In-Reply-To: <20200309210157.29860-1-repk@triplefau.lt>
On AXG platforms HHI_MIPI_CNTL0 is part of the MIPI/PCIe analog PHY
region and is not related to clock one and can be removed from it.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
---
drivers/clk/meson/axg.c | 3 ---
drivers/clk/meson/axg.h | 1 -
2 files changed, 4 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 13fc0006f63d..870e90a863fa 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -1141,7 +1141,6 @@ static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
-static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);
/* Always On (AO) domain gates */
@@ -1236,7 +1235,6 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
[CLKID_PCIE_REF] = &axg_pcie_ref.hw,
[CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
[CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
- [CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw,
[CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
[CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
[CLKID_GEN_CLK] = &axg_gen_clk.hw,
@@ -1331,7 +1329,6 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
&axg_pcie_ref,
&axg_pcie_cml_en0,
&axg_pcie_cml_en1,
- &axg_mipi_enable,
&axg_gen_clk_sel,
&axg_gen_clk_div,
&axg_gen_clk,
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 0431dabac629..fafe31739d0d 100644
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -16,7 +16,6 @@
* Register offsets from the data sheet must be multiplied by 4 before
* adding them to the base address to get the right value.
*/
-#define HHI_MIPI_CNTL0 0x00
#define HHI_GP0_PLL_CNTL 0x40
#define HHI_GP0_PLL_CNTL2 0x44
#define HHI_GP0_PLL_CNTL3 0x48
--
2.25.0
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next prev parent reply other threads:[~2020-03-09 20:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-09 21:01 [PATCH 0/2] clk: meson: axg: Remove MIPI enable clock gate Remi Pommarel
2020-03-09 21:01 ` Remi Pommarel [this message]
2020-03-09 21:01 ` [PATCH 2/2] clk: meson-axg: remove CLKID_MIPI_ENABLE Remi Pommarel
2020-03-10 8:05 ` [PATCH 0/2] clk: meson: axg: Remove MIPI enable clock gate Jerome Brunet
2021-01-04 11:42 ` Jerome Brunet
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