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X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Hanjie Lin , Victor Wan , Neil Armstrong , Kevin Hilman , linux-kernel@vger.kernel.org, Qiufang Dai , Rob Herring , Jian Hu , Xingyu Chen , Tao Zeng , Carlo Caione , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Jerome Brunet Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Hi Jianxin, On Fri, Sep 6, 2019 at 7:58 AM Jianxin Pan wrote: [...] > > also I'm a bit surprised to see no busses (like aobus, cbus, periphs, ...) here > > aren't there any busses defined in the A1 SoC implementation or are > > were you planning to add them later? > Unlike previous series,there is no Cortex-M3 AO CPU in A1, and there is no AO/EE power domain. > Most of the registers are on the apb_32b bus. aobus, cbus and periphs are not used in A1. OK, thank you for the explanation since you're going to re-send the patch anyways: can you please include the apb_32b bus? all other upstream Amlogic .dts are using the bus definitions, so that will make A1 consistent with the other SoCs Martin _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic