From: Huacai Chen <chenhuacai@gmail.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Huacai Chen <chenhuacai@loongson.cn>,
Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Peter Zijlstra <peterz@infradead.org>,
Andrew Morton <akpm@linux-foundation.org>,
David Airlie <airlied@linux.ie>,
Linus Torvalds <torvalds@linux-foundation.org>,
linux-arch <linux-arch@vger.kernel.org>,
Xuefeng Li <lixuefeng@loongson.cn>,
Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: Re: [PATCH 15/19] LoongArch: Add PCI controller support
Date: Thu, 12 Aug 2021 19:29:05 +0800 [thread overview]
Message-ID: <CAAhV-H6DCX_5cnHJHH5Bo2JjmaOkxg0Aa_VeRgv=F+avmPum7Q@mail.gmail.com> (raw)
In-Reply-To: <CAK8P3a35-46xOdVFCo=ta6x6FfU9+drERsK=OdUxR3uSRJRcQw@mail.gmail.com>
Hi, Arnd,
On Tue, Jul 6, 2021 at 6:17 PM Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Tue, Jul 6, 2021 at 6:18 AM Huacai Chen <chenhuacai@loongson.cn> wrote:
> >
> > Loongson64 based systems are PC-like systems which use PCI/PCIe as its
> > I/O bus, This patch adds the PCI host controller support for LoongArch.
> >
> > Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> > ---
> > arch/loongarch/include/asm/pci.h | 124 ++++++++++++++++++
> > arch/loongarch/pci/acpi.c | 194 ++++++++++++++++++++++++++++
> > arch/loongarch/pci/mmconfig.c | 105 +++++++++++++++
> > arch/loongarch/pci/pci-loongson.c | 130 +++++++++++++++++++
> > arch/loongarch/pci/pci.c | 207 ++++++++++++++++++++++++++++++
>
> PCI controller support should generally live in drivers/pci/controller/ and
> get reviewed by the subsystem maintainers.
>
> > +/*
> > + * This file essentially defines the interface between board specific
> > + * PCI code and LoongArch common PCI code. Should potentially put into
> > + * include/asm/pci.h file.
> > + */
> > +
> > +#include <linux/ioport.h>
> > +#include <linux/list.h>
> > +
> > +extern const struct pci_ops *__read_mostly loongarch_pci_ops;
>
> There is already an abstraction for this in the common code, don't add another.
OK, thanks.
>
> > +/*
> > + * Each pci channel is a top-level PCI bus seem by CPU. A machine with
> > + * multiple PCI channels may have multiple PCI host controllers or a
> > + * single controller supporting multiple channels.
> > + */
> > +struct pci_controller {
> > + struct list_head list;
> > + struct pci_bus *bus;
> > + struct device_node *of_node;
> > +
> > + struct pci_ops *pci_ops;
> > + struct resource *mem_resource;
> > + unsigned long mem_offset;
> > + struct resource *io_resource;
> > + unsigned long io_offset;
> > + unsigned long io_map_base;
> > + struct resource *busn_resource;
> > +
> > + unsigned int node;
> > + unsigned int index;
> > + unsigned int need_domain_info;
> > +#ifdef CONFIG_ACPI
> > + struct acpi_device *companion;
> > +#endif
> > + phys_addr_t mcfg_addr;
> > +};
> > +
> > +extern void pcibios_add_root_resources(struct list_head *resources);
> > +
> > +extern phys_addr_t mcfg_addr_init(int domain);
> > +
> > +#ifdef CONFIG_PCI_DOMAINS
> > +static inline void set_pci_need_domain_info(struct pci_controller *hose,
> > + int need_domain_info)
> > +{
> > + hose->need_domain_info = need_domain_info;
> > +}
> > +#endif /* CONFIG_PCI_DOMAINS */
>
> Just use PCI_DOMAINS unconditionally
OK, thanks.
>
> > +
> > +/*
> > + * Can be used to override the logic in pci_scan_bus for skipping
> > + * already-configured bus numbers - to be used for buggy BIOSes
> > + * or architectures with incomplete PCI setup by the loader
> > + */
> > +static inline unsigned int pcibios_assign_all_busses(void)
> > +{
> > + return 1;
> > +}
>
> Since you use ACPI, the BIOS should be responsible for assigning the
> buses, otherwise the ACPI data may be mismatched with the PCI
> device locations that the kernel sees.
>
> > +#define PCIBIOS_MIN_IO 0
>
> I think this means PCI devices can reuse ports that are reserved
> for ISA devices. Since you claim to support ISA, I think this should
> be 0x1000
OK, thanks.
>
> > +
> > +int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
> > + int reg, int len, u32 *val)
> > +{
> > + struct pci_bus *bus_tmp = pci_find_bus(domain, bus);
> > +
> > + if (bus_tmp)
> > + return bus_tmp->ops->read(bus_tmp, devfn, reg, len, val);
> > + return -EINVAL;
> > +}
> > +
> > +int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
> > + int reg, int len, u32 val)
> > +{
> > + struct pci_bus *bus_tmp = pci_find_bus(domain, bus);
> > +
> > + if (bus_tmp)
> > + return bus_tmp->ops->write(bus_tmp, devfn, reg, len, val);
> > + return -EINVAL;
> > +}
>
> This looks like you copied from arch/arm64. I think the code really
> needs to be generalized more. Maybe move the arm64 implementation
> to drivers/acpi/ so it can be shared with loongarch?
Emmm, this seems like a future story..
Huacai
>
> > +/*
> > + * We need to avoid collisions with `mirrored' VGA ports
> > + * and other strange ISA hardware, so we always want the
> > + * addresses to be allocated in the 0x000-0x0ff region
> > + * modulo 0x400.
> > + *
> > + * Why? Because some silly external IO cards only decode
> > + * the low 10 bits of the IO address. The 0x00-0xff region
> > + * is reserved for motherboard devices that decode all 16
> > + * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
> > + * but we want to try to avoid allocating at 0x2900-0x2bff
> > + * which might have be mirrored at 0x0100-0x03ff..
> > + */
> > +resource_size_t
> > +pcibios_align_resource(void *data, const struct resource *res,
> > + resource_size_t size, resource_size_t align)
> > +{
> > + struct pci_dev *dev = data;
> > + struct pci_controller *hose = dev->sysdata;
> > + resource_size_t start = res->start;
> > +
> > + if (res->flags & IORESOURCE_IO) {
> > + /* Make sure we start at our min on all hoses */
> > + if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
> > + start = PCIBIOS_MIN_IO + hose->io_resource->start;
> > +
> > + /*
> > + * Put everything into 0x00-0xff region modulo 0x400
> > + */
> > + if (start & 0x300)
> > + start = (start + 0x3ff) & ~0x3ff;
> > + } else if (res->flags & IORESOURCE_MEM) {
> > + /* Make sure we start at our min on all hoses */
> > + if (start < PCIBIOS_MIN_MEM)
> > + start = PCIBIOS_MIN_MEM;
> > + }
> > +
> > + return start;
> > +}
>
> Same here, please don't add another copy of this function.
>
>
> Arnd
next prev parent reply other threads:[~2021-08-12 11:29 UTC|newest]
Thread overview: 131+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-06 4:18 [PATCH 00/19] arch: Add basic LoongArch support Huacai Chen
2021-07-06 4:18 ` [PATCH 01/19] LoongArch: Add elf-related definitions Huacai Chen
2021-07-06 4:18 ` [PATCH 02/19] LoongArch: Add writecombine support for drm Huacai Chen
2021-07-06 4:18 ` [PATCH 03/19] LoongArch: Add build infrastructure Huacai Chen
2021-07-06 10:12 ` Arnd Bergmann
2021-07-19 1:26 ` Huacai Chen
2021-07-19 7:43 ` Arnd Bergmann
2021-07-19 13:02 ` Huacai Chen
2021-07-06 10:35 ` Arnd Bergmann
2021-07-07 0:00 ` Randy Dunlap
2021-07-19 1:28 ` Huacai Chen
2021-07-06 4:18 ` [PATCH 05/19] LoongArch: Add boot and setup routines Huacai Chen
2021-07-06 10:16 ` Arnd Bergmann
2021-07-27 11:53 ` Huacai Chen
2021-07-27 12:40 ` Arnd Bergmann
2021-07-27 12:51 ` Ard Biesheuvel
2021-07-27 13:14 ` Arnd Bergmann
2021-07-27 16:22 ` Ard Biesheuvel
2021-07-27 17:53 ` Arnd Bergmann
2021-07-28 10:24 ` Huacai Chen
2021-07-06 10:55 ` Arnd Bergmann
2021-07-06 4:18 ` [PATCH 06/19] LoongArch: Add exception/interrupt handling Huacai Chen
2021-07-06 10:16 ` Arnd Bergmann
2021-07-06 10:56 ` Arnd Bergmann
2021-07-06 11:06 ` Peter Zijlstra
2021-07-07 13:56 ` Nicholas Piggin
2021-07-27 14:10 ` Peter Zijlstra
2021-07-27 15:08 ` Arnd Bergmann
2021-07-28 10:16 ` Huacai Chen
2021-07-28 12:23 ` Arnd Bergmann
2021-07-06 4:18 ` [PATCH 07/19] LoongArch: Add process management Huacai Chen
2021-07-06 10:16 ` Arnd Bergmann
2021-07-06 10:57 ` Arnd Bergmann
2021-07-06 11:09 ` Peter Zijlstra
2021-08-12 11:17 ` Huacai Chen
2021-08-12 12:29 ` Arnd Bergmann
2021-08-12 12:51 ` Huacai Chen
2021-07-06 4:18 ` [PATCH 08/19] LoongArch: Add memory management Huacai Chen
2021-07-06 10:16 ` Arnd Bergmann
2021-07-06 10:57 ` Arnd Bergmann
2021-08-12 11:20 ` Huacai Chen
2021-08-16 1:57 ` Guo Ren
2021-08-16 3:31 ` Huacai Chen
2021-07-06 4:18 ` [PATCH 09/19] LoongArch: Add system call support Huacai Chen
2021-07-06 10:17 ` Arnd Bergmann
2021-07-06 10:58 ` Arnd Bergmann
2021-07-07 4:24 ` Huacai Chen
2021-07-07 6:44 ` Arnd Bergmann
2021-07-07 7:00 ` Huacai Chen
2021-07-09 8:44 ` Huacai Chen
2021-07-06 13:51 ` Thomas Gleixner
2021-07-07 4:27 ` Huacai Chen
2021-08-12 12:40 ` Huacai Chen
2021-07-06 4:18 ` [PATCH 10/19] LoongArch: Add signal handling support Huacai Chen
2021-07-06 10:17 ` Arnd Bergmann
2021-07-06 10:59 ` Arnd Bergmann
2021-07-08 13:04 ` Huacai Chen
2021-07-08 13:23 ` Arnd Bergmann
2021-07-09 9:24 ` Huacai Chen
2021-07-09 10:22 ` Arnd Bergmann
2021-07-09 14:49 ` Eric W. Biederman
2021-07-09 15:59 ` Arnd Bergmann
2021-08-26 16:43 ` Xi Ruoyao
2021-08-27 4:23 ` Huacai Chen
2021-08-27 4:27 ` Xi Ruoyao
2021-07-06 4:18 ` [PATCH 11/19] LoongArch: Add elf and module support Huacai Chen
2021-07-06 4:18 ` [PATCH 12/19] LoongArch: Add misc common routines Huacai Chen
2021-07-06 10:17 ` Arnd Bergmann
2021-07-06 11:00 ` Arnd Bergmann
2021-07-23 10:41 ` Huacai Chen
2021-07-23 11:43 ` Arnd Bergmann
2021-07-24 12:53 ` Huacai Chen
2021-07-06 4:18 ` [PATCH 13/19] LoongArch: Add some library functions Huacai Chen
2021-07-06 10:17 ` Arnd Bergmann
2021-07-06 11:00 ` Arnd Bergmann
2021-08-12 11:22 ` Huacai Chen
2021-07-06 4:18 ` [PATCH 14/19] LoongArch: Add 64-bit Loongson platform Huacai Chen
2021-07-06 4:18 ` [PATCH 15/19] LoongArch: Add PCI controller support Huacai Chen
2021-07-06 10:17 ` Arnd Bergmann
2021-07-06 11:01 ` Arnd Bergmann
2021-08-12 11:29 ` Huacai Chen [this message]
2021-07-06 4:18 ` [PATCH 16/19] LoongArch: Add VDSO and VSYSCALL support Huacai Chen
2021-07-06 10:17 ` Arnd Bergmann
2021-07-06 11:02 ` Arnd Bergmann
2021-08-12 11:31 ` Huacai Chen
2021-07-06 4:18 ` [PATCH 17/19] LoongArch: Add multi-processor (SMP) support Huacai Chen
2021-07-06 10:17 ` Arnd Bergmann
2021-07-06 11:03 ` Arnd Bergmann
2021-07-06 11:32 ` Peter Zijlstra
2021-08-12 11:39 ` Huacai Chen
2021-07-06 11:56 ` Peter Zijlstra
2021-07-06 13:48 ` Peter Zijlstra
2021-08-12 11:41 ` Huacai Chen
2021-07-06 13:52 ` Peter Zijlstra
2021-07-06 4:18 ` [PATCH 18/19] LoongArch: Add Non-Uniform Memory Access (NUMA) support Huacai Chen
2021-07-06 10:18 ` Arnd Bergmann
2021-07-06 11:03 ` Arnd Bergmann
2021-08-12 11:46 ` Huacai Chen
2021-08-12 12:48 ` Arnd Bergmann
2021-07-06 4:18 ` [PATCH 19/19] LoongArch: Add Loongson-3 default config file Huacai Chen
2021-07-06 10:18 ` Arnd Bergmann
2021-07-06 11:04 ` Arnd Bergmann
2021-08-12 11:58 ` Huacai Chen
2021-08-12 12:50 ` Arnd Bergmann
2021-07-06 10:11 ` [PATCH 00/19] arch: Add basic LoongArch support Arnd Bergmann
2021-07-07 3:04 ` Huacai Chen
2021-07-07 7:28 ` Arnd Bergmann
2021-07-29 16:48 ` Huacai Chen
2021-07-30 20:50 ` Arnd Bergmann
2021-07-06 10:33 ` Arnd Bergmann
[not found] ` <20210706041820.1536502-5-chenhuacai@loongson.cn>
2021-07-06 10:16 ` [PATCH 04/19] LoongArch: Add common headers Arnd Bergmann
2021-08-12 11:05 ` Huacai Chen
2021-08-12 12:45 ` Arnd Bergmann
2021-08-13 3:30 ` Huacai Chen
2021-08-13 7:05 ` Arnd Bergmann
2021-08-13 8:14 ` Huacai Chen
2021-08-13 9:08 ` Arnd Bergmann
2021-08-14 2:50 ` Huacai Chen
2021-08-15 8:56 ` Arnd Bergmann
2021-08-16 4:10 ` Huacai Chen
2021-08-18 9:38 ` Arnd Bergmann
2021-08-20 4:00 ` Huacai Chen
2021-08-20 7:55 ` Arnd Bergmann
2021-08-21 8:16 ` Huacai Chen
2021-07-06 10:54 ` Arnd Bergmann
2021-07-06 10:57 ` Peter Zijlstra
2021-07-06 11:23 ` Peter Zijlstra
2021-07-06 12:59 ` Arnd Bergmann
2021-07-06 13:20 ` Peter Zijlstra
2021-07-06 13:37 ` Peter Zijlstra
2021-07-06 11:59 ` Peter Zijlstra
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAAhV-H6DCX_5cnHJHH5Bo2JjmaOkxg0Aa_VeRgv=F+avmPum7Q@mail.gmail.com' \
--to=chenhuacai@gmail.com \
--cc=airlied@linux.ie \
--cc=akpm@linux-foundation.org \
--cc=arnd@arndb.de \
--cc=chenhuacai@loongson.cn \
--cc=jiaxun.yang@flygoat.com \
--cc=linux-arch@vger.kernel.org \
--cc=lixuefeng@loongson.cn \
--cc=luto@kernel.org \
--cc=peterz@infradead.org \
--cc=tglx@linutronix.de \
--cc=torvalds@linux-foundation.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).