From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Nicolas Boichat <drinkcat@chromium.org>
Cc: Rob Herring <robh@kernel.org>,
srv_heupstream <srv_heupstream@mediatek.com>,
James Liao <jamesjj.liao@mediatek.com>,
lkml <linux-kernel@vger.kernel.org>,
Fan Chen <fan.chen@mediatek.com>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v5 06/14] soc: mediatek: Refactor clock control
Date: Wed, 19 Jun 2019 17:19:47 +0800 [thread overview]
Message-ID: <1560935987.2158.8.camel@mtksdaap41> (raw)
In-Reply-To: <CANMq1KCxhnn+fKaxS1RbpYYJ7pcXzD8XkqTBJHiauHbfrYVTGA@mail.gmail.com>
On Tue, 2019-03-19 at 20:02 +0800, Nicolas Boichat wrote:
> On Tue, Mar 19, 2019 at 4:02 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> >
> > Put clock enable and disable control in separate function.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> > drivers/soc/mediatek/mtk-scpsys.c | 49 ++++++++++++++++++++-----------
> > 1 file changed, 32 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> > index 765ad4a5e5df..3e9be07a2627 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -208,6 +208,33 @@ static int scpsys_regulator_disable(struct scp_domain *scpd)
> > return regulator_disable(scpd->supply);
> > }
> >
> > +static int scpsys_clk_enable(struct clk *clk[], int max_num)
> > +{
> > + int i, ret = 0;
> > +
> > + for (i = 0; i < max_num && clk[i]; i++) {
> > + ret = clk_prepare_enable(clk[i]);
> > + if (ret) {
> > + for (--i; i >= 0; i--)
> > + clk_disable_unprepare(clk[i]);
>
> Would it be simpler to just call scpsys_clk_disable(clk, i) ?
>
OK, I'll try.
> > +
> > + break;
> > + }
> > + }
> > +
> > + return ret;
> > +}
>
> Maybe not for this series, but could you use clk_bulk_prepare_enable
> instead? The only issue is that it'd still call clk_prepare_enable on
> NULL clocks, but that does nothing, so it's just a little less
> efficient...
>
OK, I'll try after this series.
> > +
> > +static void scpsys_clk_disable(struct clk *clk[], int max_num)
> > +{
> > + int i;
> > +
> > + for (i = max_num - 1; i >= 0; i--) {
> > + if (clk[i])
>
> if test not needed, clk_disable_unprepare ignores NULL parameters.
>
You're right. Supposed it's not needed, I'll test.
> > + clk_disable_unprepare(clk[i]);
> > + }
> > +}
>
> ditto: clk_bulk_disable_unprepare
>
> > +
> > static int scpsys_power_on(struct generic_pm_domain *genpd)
> > {
> > struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> > @@ -216,21 +243,14 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> > u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
> > u32 val;
> > int ret, tmp;
> > - int i;
> >
> > ret = scpsys_regulator_enable(scpd);
> > if (ret < 0)
> > return ret;
> >
> > - for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
> > - ret = clk_prepare_enable(scpd->clk[i]);
> > - if (ret) {
> > - for (--i; i >= 0; i--)
> > - clk_disable_unprepare(scpd->clk[i]);
> > -
> > - goto err_clk;
> > - }
> > - }
> > + ret = scpsys_clk_enable(scpd->clk, MAX_CLKS);
> > + if (ret)
> > + goto err_clk;
> >
> > val = readl(ctl_addr);
> > val |= PWR_ON_BIT;
> > @@ -283,10 +303,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> > return 0;
> >
> > err_pwr_ack:
> > - for (i = MAX_CLKS - 1; i >= 0; i--) {
> > - if (scpd->clk[i])
> > - clk_disable_unprepare(scpd->clk[i]);
> > - }
> > + scpsys_clk_disable(scpd->clk, MAX_CLKS);
> > err_clk:
> > scpsys_regulator_disable(scpd);
> >
> > @@ -303,7 +320,6 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> > u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
> > u32 val;
> > int ret, tmp;
> > - int i;
> >
> > if (scpd->data->bus_prot_mask) {
> > ret = mtk_infracfg_set_bus_protection(scp->infracfg,
> > @@ -344,8 +360,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> > if (ret < 0)
> > goto out;
> >
> > - for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
> > - clk_disable_unprepare(scpd->clk[i]);
> > + scpsys_clk_disable(scpd->clk, MAX_CLKS);
> >
> > ret = scpsys_regulator_disable(scpd);
> > if (ret < 0)
> > --
> > 2.18.0
> >
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next prev parent reply other threads:[~2019-06-19 9:20 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-19 8:01 [PATCH v5 00/14] Mediatek MT8183 scpsys support Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 01/14] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 02/14] dt-bindings: soc: Add MT8183 power dt-bindings Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 03/14] soc: mediatek: Switch to SPDX license identifier Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 04/14] soc: mediatek: Refactor polling timeout and documentation Weiyi Lu
2019-03-19 11:45 ` Nicolas Boichat
2019-06-19 9:11 ` Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 05/14] soc: mediatek: Refactor regulator control Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 06/14] soc: mediatek: Refactor clock control Weiyi Lu
2019-03-19 12:02 ` Nicolas Boichat
2019-06-19 9:19 ` Weiyi Lu [this message]
2019-03-19 8:01 ` [PATCH v5 07/14] soc: mediatek: Refactor sram control Weiyi Lu
2019-03-19 12:07 ` Nicolas Boichat
2019-06-19 9:30 ` Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 08/14] soc: mediatek: Refactor bus protection control Weiyi Lu
2019-03-19 12:09 ` Nicolas Boichat
2019-06-19 9:31 ` Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 09/14] soc: mediatek: Add basic_clk_name to scp_power_data Weiyi Lu
2019-03-21 6:02 ` Nicolas Boichat
2019-06-19 9:36 ` Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 10/14] soc: mediatek: Add multiple step bus protection control Weiyi Lu
2019-03-21 5:57 ` Nicolas Boichat
2019-06-19 9:43 ` Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 11/14] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 12/14] soc: mediatek: Add extra sram control Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 13/14] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 14/14] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
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