From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
Leo Li <leoyang.li@nxp.com>
Cc: Roy Zang <roy.zang@nxp.com>, "Z.q. Hou" <zhiqiang.hou@nxp.com>,
Mingkai Hu <mingkai.hu@nxp.com>,
"M.h. Lian" <minghuan.lian@nxp.com>
Subject: [PATCHv3 4/5] PCI: dwc: fix 4GiB outbound window size truncated to zero issue
Date: Tue, 18 Dec 2018 04:19:43 +0000 [thread overview]
Message-ID: <20181218041956.41809-5-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20181218041956.41809-1-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The current type of mem_size is 'u32', so when resource_size()
return 4G it will be truncated to zero. This patch fix it by
changing its type to 'u64'.
Fixes: 340cba6092c2 ("pci: Add PCIe driver for Samsung Exynos")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
V3:
- No change
drivers/pci/controller/dwc/pcie-designware.c | 4 ++--
drivers/pci/controller/dwc/pcie-designware.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 2153956a0b20..7ac5989c23ef 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -106,7 +106,7 @@ static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
int type, u64 cpu_addr,
- u64 pci_addr, u32 size)
+ u64 pci_addr, u64 size)
{
u32 retries, val;
@@ -141,7 +141,7 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
}
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
- u64 cpu_addr, u64 pci_addr, u32 size)
+ u64 cpu_addr, u64 pci_addr, u64 size)
{
u32 retries, val;
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 0989d880ac46..25604387d13e 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -157,7 +157,7 @@ struct pcie_port {
u32 io_size;
u64 mem_base;
phys_addr_t mem_bus_addr;
- u32 mem_size;
+ u64 mem_size;
struct resource *cfg;
struct resource *io;
struct resource *mem;
@@ -242,7 +242,7 @@ int dw_pcie_link_up(struct dw_pcie *pci);
int dw_pcie_wait_for_link(struct dw_pcie *pci);
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
int type, u64 cpu_addr, u64 pci_addr,
- u32 size);
+ u64 size);
int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
u64 cpu_addr, enum dw_pcie_as_type as_type);
void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
--
2.17.1
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next prev parent reply other threads:[~2018-12-18 4:20 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-18 4:19 [PATCHv3 0/5] PCI: dwc: add prefetchable memory range support Z.q. Hou
2018-12-18 4:19 ` [PATCHv3 1/5] ARM: dts: ls1021a: add num-viewport property for PCIe DT nodes Z.q. Hou
2019-01-11 7:30 ` Shawn Guo
2018-12-18 4:19 ` [PATCHv3 2/5] arm64: dts: layerscape: " Z.q. Hou
2019-01-11 7:30 ` Shawn Guo
2018-12-18 4:19 ` [PATCHv3 3/5] PCI: dwc: fix potential memory leak Z.q. Hou
2018-12-18 4:19 ` Z.q. Hou [this message]
2018-12-18 4:19 ` [PATCHv3 5/5] PCI: dwc: add prefetchable memory range support Z.q. Hou
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