From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9408FC282C4 for ; Tue, 12 Feb 2019 16:30:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5991D20842 for ; Tue, 12 Feb 2019 16:30:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="OcylCDid" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5991D20842 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=atomide.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1Pco45NvFC1xSGGhmSjQYaodiH2QDlqgKdBqWZI0a0E=; b=OcylCDidmEpsh2 NloDVJLrA4nLXBUQtBq7KR08jYik3eGUvWFU451Pfs9z/yCb8fsUf4lLP36f3uODCHbm3r9+ZNnUE 2wlw5Z2YrkcZjyDBxp297kMFBG80DVhDYfk7jKcqzACNMoGDAI8wDLOFsbLNHqX12uqE1baaDh+Wi YYYtttFTsyFPL0Oy9Odt4jRxXKm+il6p6WkdD5tC+FirEW+TpLdxgQ+F4F2QAWjAHAm1oe/Lf8N59 imjcQf8GmiB4/hm7vW72s+T7sf3pPJGgjSxRoIju6xpVqVHX6Mlp/GeQLrpc1K2qlM69Qwm/xrMg1 ZkWvvGjUEOS9R5vHYFPg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gtax2-0000tH-UQ; Tue, 12 Feb 2019 16:30:28 +0000 Received: from muru.com ([72.249.23.125]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gtawx-0000sT-Oh for linux-arm-kernel@lists.infradead.org; Tue, 12 Feb 2019 16:30:27 +0000 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 319F6803A; Tue, 12 Feb 2019 16:30:31 +0000 (UTC) Date: Tue, 12 Feb 2019 08:30:18 -0800 From: Tony Lindgren To: Lokesh Vutla Subject: Re: [PATCH v5 05/10] dt-bindings: irqchip: Introduce TISCI Interrupt router bindings Message-ID: <20190212163018.GL5720@atomide.com> References: <20190212074237.2875-1-lokeshvutla@ti.com> <20190212074237.2875-6-lokeshvutla@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190212074237.2875-6-lokeshvutla@ti.com> User-Agent: Mutt/1.11.2 (2019-01-07) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190212_083023_841122_600CBE4C X-CRM114-Status: GOOD ( 11.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Device Tree Mailing List , jason@lakedaemon.net, Peter Ujfalusi , marc.zyngier@arm.com, Sekhar Nori , linux-kernel@vger.kernel.org, Tero Kristo , Rob Herring , Santosh Shilimkar , tglx@linutronix.de, Linux ARM Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, * Lokesh Vutla [190212 07:43]: > +The Interrupt Router (INTR) module provides a mechanism to route M > +interrupt inputs to N interrupt outputs, where all M inputs are selectable > +to be driven per N output. There is one register per output (MUXCNTL_N) that > +controls the selection. > + > + > + Interrupt Router > + +----------------------+ > + | Inputs Outputs | > + +-------+ | +------+ | > + | GPIO |----------->| | irq0 | | Host IRQ > + +-------+ | +------+ | controller > + | . +-----+ | +-------+ > + +-------+ | . | 0 | |----->| IRQ | > + | INTA |----------->| . +-----+ | +-------+ > + +-------+ | . . | > + | +------+ . | > + | | irqM | +-----+ | > + | +------+ | N | | > + | +-----+ | > + +----------------------+ Is this always one-to-one mapping or can the same interrupt be routed to multiple targets like to the SoC and some coprocessor? > +Configuration of these MUXCNTL_N registers is done by a system controller > +(like the Device Memory and Security Controller on K3 AM654 SoC). System > +controller will keep track of the used and unused registers within the Router. > +Driver should request the system controller to get the range of GIC IRQs > +assigned to the requesting hosts. It is the drivers responsibility to keep > +track of Host IRQs. > + > +Communication between the host processor running an OS and the system > +controller happens through a protocol called TI System Control Interface > +(TISCI protocol). For more details refer: > +Documentation/devicetree/bindings/arm/keystone/ti,sci.txt Care to describe a bit why the interrupts need to be routed by a system controller? Regards, Tony _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel