From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, Yan Markman <ymarkman@marvell.com>,
Antoine Tenart <antoine.tenart@bootlin.com>,
Grzegorz Jaszczyk <jaz@semihalf.com>,
Gregory Clement <gregory.clement@bootlin.com>,
Maxime Chevallier <maxime.chevallier@bootlin.com>,
Nadav Haklai <nadavh@marvell.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Stefan Chulski <stefanc@marvell.com>,
Marcin Wojtas <mw@semihalf.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 14/20] arm64: dts: marvell: Externalize PCIe macros from CP11x file
Date: Tue, 6 Aug 2019 16:54:54 +0200 [thread overview]
Message-ID: <20190806145500.24109-15-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
PCIe macros are specific to CP110 and will not fit CP115
constraints. To keep the same way the files are organized, just move
some macros out of the CP11x generic file and define them directly in
SoC DTSI, instead of defining single addresses in the SoC DTSI and
reusing them in macros.
In the end:
* CP11X_PCIE_MEM_BASE SoC define is dropped
* CP11X_PCIEx_MEM_BASE is moved out of the generic DT to be put in the
SoC files as it replaces the above definition.
* As the CP11X_PCIEx_MEM_SIZE macro is also subject to change with
newer SoCs, we put it in the SoC files as well.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++--
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 12 ++++++++----
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 9 ++++-----
3 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index ac28903ea409..293403a1a333 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -19,7 +19,8 @@
*/
#define CP11X_NAME cp0
#define CP11X_BASE f2000000
-#define CP11X_PCIE_MEM_BASE 0xf6000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f2600000
#define CP11X_PCIE1_BASE f2620000
#define CP11X_PCIE2_BASE f2640000
@@ -28,7 +29,8 @@
#undef CP11X_NAME
#undef CP11X_BASE
-#undef CP11X_PCIE_MEM_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index 902eed571bcc..ee67c70bf02e 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -21,7 +21,8 @@
*/
#define CP11X_NAME cp0
#define CP11X_BASE f2000000
-#define CP11X_PCIE_MEM_BASE 0xf6000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f2600000
#define CP11X_PCIE1_BASE f2620000
#define CP11X_PCIE2_BASE f2640000
@@ -30,7 +31,8 @@
#undef CP11X_NAME
#undef CP11X_BASE
-#undef CP11X_PCIE_MEM_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
@@ -40,7 +42,8 @@
*/
#define CP11X_NAME cp1
#define CP11X_BASE f4000000
-#define CP11X_PCIE_MEM_BASE 0xfa000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f4600000
#define CP11X_PCIE1_BASE f4620000
#define CP11X_PCIE2_BASE f4640000
@@ -49,7 +52,8 @@
#undef CP11X_NAME
#undef CP11X_BASE
-#undef CP11X_PCIE_MEM_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 7d1ab097453d..9dcf16beabf5 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -10,8 +10,7 @@
#include "armada-common.dtsi"
-#define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000))
-#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
+#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
/ {
/*
@@ -507,7 +506,7 @@
bus-range = <0 0xff>;
/* non-prefetchable memory */
- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
@@ -531,7 +530,7 @@
bus-range = <0 0xff>;
/* non-prefetchable memory */
- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
@@ -556,7 +555,7 @@
bus-range = <0 0xff>;
/* non-prefetchable memory */
- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
--
2.20.1
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next prev parent reply other threads:[~2019-08-06 14:57 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-06 14:54 [PATCH 00/20] Add new Marvell CN9130 SoC support Miquel Raynal
2019-08-06 14:54 ` [PATCH 01/20] arm64: dts: marvell: Enumerate the first AP806 syscon Miquel Raynal
2019-08-06 14:54 ` [PATCH 02/20] arm64: dts: marvell: Add AP806-dual missing CPU clocks Miquel Raynal
2019-08-06 14:54 ` [PATCH 03/20] dt-bindings: ap80x: replace AP806 with AP80x Miquel Raynal
2019-08-21 19:32 ` Rob Herring
2019-08-06 14:54 ` [PATCH 04/20] MAINTAINERS: Add new Marvell CN9130-based files to track Miquel Raynal
2019-08-06 14:54 ` [PATCH 05/20] arm64: dts: marvell: Prepare the introduction of AP807 based SoCs Miquel Raynal
2019-08-27 15:20 ` Gregory CLEMENT
2019-08-06 14:54 ` [PATCH 06/20] arm64: dts: marvell: Move clocks to AP806 specific file Miquel Raynal
2019-08-06 14:54 ` [PATCH 07/20] arm64: dts: marvell: Add support for AP807/AP807-quad Miquel Raynal
2019-08-06 14:54 ` [PATCH 08/20] arm64: dts: marvell: Add AP806-dual cache description Miquel Raynal
2019-08-06 14:54 ` [PATCH 09/20] arm64: dts: marvell: Add AP806-quad " Miquel Raynal
2019-08-06 14:54 ` [PATCH 10/20] arm64: dts: marvell: Add AP807-quad " Miquel Raynal
2019-08-06 14:54 ` [PATCH 11/20] arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment Miquel Raynal
2019-08-06 14:54 ` [PATCH 12/20] arm64: dts: marvell: Prepare the introduction of CP115 Miquel Raynal
2019-08-06 14:54 ` [PATCH 13/20] arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file Miquel Raynal
2019-08-06 14:54 ` Miquel Raynal [this message]
2019-08-06 14:54 ` [PATCH 15/20] arm64: dts: marvell: Add support for CP115 Miquel Raynal
2019-08-06 14:54 ` [PATCH 16/20] dt-bindings: marvell: Declare the CN913x SoC compatibles Miquel Raynal
2019-08-21 19:37 ` Rob Herring
2019-08-24 11:30 ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 17/20] arm64: dts: marvell: Add support for Marvell CN9130 SoC support Miquel Raynal
2019-08-06 14:54 ` [PATCH 18/20] arm64: dts: marvell: Add support for Marvell CN9130-DB Miquel Raynal
2019-08-06 14:54 ` [PATCH 19/20] arm64: dts: marvell: Add support for Marvell CN9131-DB Miquel Raynal
2019-08-06 14:55 ` [PATCH 20/20] arm64: dts: marvell: Add support for Marvell CN9132-DB Miquel Raynal
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