From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Grzegorz Jaszczyk <jaz@semihalf.com>
Cc: bhelgaas@google.com, linux-pci@vger.kernel.org, mw@semihalf.com,
linux-arm-kernel@lists.infradead.org,
thomas.petazzoni@bootlin.com
Subject: Re: [PATCH v2] PCI: aardvark: fix big endian support
Date: Thu, 17 Oct 2019 13:43:59 +0100 [thread overview]
Message-ID: <20191017124359.GA19340@e121166-lin.cambridge.arm.com> (raw)
In-Reply-To: <1563279127-30678-1-git-send-email-jaz@semihalf.com>
On Tue, Jul 16, 2019 at 02:12:07PM +0200, Grzegorz Jaszczyk wrote:
> Initialise every not-byte wide fields of emulated pci bridge config
> space with proper cpu_to_le* macro. This is required since the structure
> describing config space of emulated bridge assumes little-endian
> convention.
>
> Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
> ---
> v1->v2
> - add missing cpu_to_le32 for class_revison assignment (issues found by
> Thomas Petazzoni and also detected by Sparse tool).
>
> drivers/pci/controller/pci-aardvark.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
Applied to pci/aardvark, thanks.
Lorenzo
> diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
> index 134e030..178e92f 100644
> --- a/drivers/pci/controller/pci-aardvark.c
> +++ b/drivers/pci/controller/pci-aardvark.c
> @@ -479,18 +479,20 @@ static void advk_sw_pci_bridge_init(struct advk_pcie *pcie)
> {
> struct pci_bridge_emul *bridge = &pcie->bridge;
>
> - bridge->conf.vendor = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff;
> - bridge->conf.device = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16;
> + bridge->conf.vendor =
> + cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
> + bridge->conf.device =
> + cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
> bridge->conf.class_revision =
> - advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff;
> + cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
>
> /* Support 32 bits I/O addressing */
> bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
> bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
>
> /* Support 64 bits memory pref */
> - bridge->conf.pref_mem_base = PCI_PREF_RANGE_TYPE_64;
> - bridge->conf.pref_mem_limit = PCI_PREF_RANGE_TYPE_64;
> + bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
> + bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
>
> /* Support interrupt A for MSI feature */
> bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
> --
> 2.7.4
>
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prev parent reply other threads:[~2019-10-17 12:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-16 12:12 [PATCH v2] PCI: aardvark: fix big endian support Grzegorz Jaszczyk
2019-09-30 8:17 ` Grzegorz Jaszczyk
2019-09-30 14:39 ` Lorenzo Pieralisi
2019-10-04 8:38 ` Grzegorz Jaszczyk
2019-10-17 12:43 ` Lorenzo Pieralisi [this message]
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