From: Thierry Reding <thierry.reding@gmail.com>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
mmaddireddy@nvidia.com, kthota@nvidia.com,
gustavo.pimentel@synopsys.com, linux-kernel@vger.kernel.org,
kishon@ti.com, linux-tegra@vger.kernel.org, robh+dt@kernel.org,
linux-pci@vger.kernel.org, bhelgaas@google.com,
andrew.murray@arm.com, jonathanh@nvidia.com,
linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: Re: [PATCH 6/6] arm64: tegra: Add support for PCIe endpoint mode in P2972-0000 platform
Date: Fri, 22 Nov 2019 14:25:33 +0100 [thread overview]
Message-ID: <20191122132533.GD1315704@ulmo> (raw)
In-Reply-To: <20191122104505.8986-7-vidyas@nvidia.com>
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On Fri, Nov 22, 2019 at 04:15:05PM +0530, Vidya Sagar wrote:
> Add endpoint mode support for PCIe C5 controller in P2972-0000 platform
> with information about supplies, PHY, PERST GPIO and GPIO that controls
> PCIe reference clock coming from the host system.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> .../boot/dts/nvidia/tegra194-p2972-0000.dts | 29 +++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
> index 7eb64b816e08..58c3a9677bc8 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
> +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
> @@ -43,6 +43,19 @@
>
> gpio@c2f0000 {
> status = "okay";
> + /*
> + * Change the below node's status to 'okay' when
> + * PCIe C5 controller is enabled to operate in endpoint
> + * to allow REFCLK from the host system to flow into
> + * the controller.
> + */
> + pex-refclk-sel-high {
> + gpio-hog;
> + output-high;
> + gpios = <TEGRA194_AON_GPIO(AA, 5) 0>;
> + label = "pex_refclk_sel_high";
> + status = "disabled";
> + };
Why don't we put this into the PCIe controller's node as a reference to
that GPIO? Seems like the controller would know exactly when this pin
needs to go high or low, so why does it have to be a hog?
Thierry
> };
>
> pwm@c340000 {
> @@ -144,6 +157,22 @@
> "p2u-5", "p2u-6", "p2u-7";
> };
>
> + pcie_ep@141a0000 {
> + status = "disabled";
> +
> + vddio-pex-ctl-supply = <&vdd_1v8ao>;
> +
> + nvidia,pex-rst-gpio = <&gpio TEGRA194_MAIN_GPIO(GG, 1)
> + GPIO_ACTIVE_LOW>;
> +
> + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
> + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
> + <&p2u_nvhs_6>, <&p2u_nvhs_7>;
> +
> + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
> + "p2u-5", "p2u-6", "p2u-7";
> + };
> +
> fan: fan {
> compatible = "pwm-fan";
> pwms = <&pwm4 0 45334>;
> --
> 2.17.1
>
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next prev parent reply other threads:[~2019-11-22 13:25 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-22 10:44 [PATCH 0/6] Add support for PCIe endpoint mode in Tegra194 Vidya Sagar
2019-11-22 10:45 ` [PATCH 1/6] soc/tegra: bpmp: Update ABI header Vidya Sagar
2019-11-22 10:45 ` [PATCH 2/6] dt-bindings: PCI: tegra: Add DT support for PCIe EP nodes in Tegra194 Vidya Sagar
2019-11-22 13:19 ` Thierry Reding
2019-11-25 7:23 ` Vidya Sagar
2019-11-25 7:33 ` Thierry Reding
2019-11-25 11:52 ` Gustavo Pimentel
2019-11-29 13:26 ` Vidya Sagar
2019-12-05 9:57 ` Vidya Sagar
2019-12-04 21:43 ` Rob Herring
2019-11-22 10:45 ` [PATCH 3/6] PCI: tegra: Add support for PCIe endpoint mode " Vidya Sagar
2019-11-26 21:37 ` Bjorn Helgaas
2019-11-29 13:22 ` Vidya Sagar
2019-11-22 10:45 ` [PATCH 4/6] arm64: tegra: Add PCIe endpoint controllers nodes for Tegra194 Vidya Sagar
2019-11-22 10:45 ` [PATCH 5/6] arm64: tegra: Enable GPIO controllers nodes for P2972-0000 platform Vidya Sagar
2019-11-22 13:20 ` Thierry Reding
2019-11-25 6:55 ` Vidya Sagar
2019-11-22 10:45 ` [PATCH 6/6] arm64: tegra: Add support for PCIe endpoint mode in " Vidya Sagar
2019-11-22 13:25 ` Thierry Reding [this message]
2019-11-25 7:00 ` Vidya Sagar
2019-11-25 7:25 ` Thierry Reding
2019-11-25 7:33 ` Vidya Sagar
2019-11-25 7:37 ` Thierry Reding
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